公开(公告)号：US06294433B1

公开(公告)日：2001-09-25

申请号：US09501560

申请日：2000-02-09

Applicant: Scott D. Luning

Inventor： Scott D. Luning

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L29/7833

Abstract: The present invention is directed to a method of forming source/drain regions in a semiconductor device and a novel device structure. In one illustrative embodiment, the method involves forming a gate stack comprised of a gate electrode above a semiconducting substrate, and performing first and second ion implantation processes to form first and second doped regions in said substrate. The method continues with forming a masking layer above at least the gate electrode, performing a third ion implantation process after the masking layer is formed to create a third doped region in the substrate, and annealing the doped regions. In one illustrative embodiment, a semiconductor device includes a gate stack formed above a substrate, and a plurality of source/drain regions formed in the substrate, the source/drain regions having a junction depth that ranges from approximately 2000-2500 Å.

Abstract translation: 本发明涉及一种在半导体器件中形成源极/漏极区域的方法和新颖的器件结构。 在一个说明性实施例中，该方法包括在半导体衬底上形成由栅极电极组成的栅极堆叠，以及执行第一和第二离子注入工艺以在所述衬底中形成第一和第二掺杂区域。 该方法继续在至少栅电极之上形成掩模层，在形成掩模层之后执行第三离子注入工艺，以在衬底中形成第三掺杂区域，并退火掺杂区域。 在一个说明性实施例中，半导体器件包括形成在衬底上的栅叠层和形成在衬底中的多个源极/漏极区，源/漏区具有约2000-2500的结深度。

公开(公告)号：US6005279A

公开(公告)日：1999-12-21

申请号：US993883

申请日：1997-12-18

Applicant: Scott D. Luning

Inventor： Scott D. Luning

IPC: H01L21/762 ,  H01L29/00

CPC classification number: H01L21/76224

Abstract: An insulating trench isolation structure is formed in a semiconductor substrate with a spacer overlying the trench edge to prevent oxide loss during subsequent etching, thereby preventing junction leakage, particulary upon silicidation. Embodiments include providing a step in the trench fill and forming the nitride spacer during gate electrode sidewall spacer formation. The protective nitride spacer etches more slowly than oxide and, hence, remains after subsequent oxide etching and cleaning.

Abstract translation: 绝缘沟槽隔离结构形成在具有覆盖沟槽边缘的间隔物的半导体衬底中，以防止在随后的蚀刻期间的氧化物损失，从而防止结露，特别是硅化。 实施例包括在栅极电极侧壁间隔物形成期间提供沟槽填充中的步骤和形成氮化物间隔物。 保护性氮化物间隔物比氧化物缓慢蚀刻，因此在随后的氧化物蚀刻和清洁之后保留。

公开(公告)号：US5989963A

公开(公告)日：1999-11-23

申请号：US897804

申请日：1997-07-21

Applicant: Scott D. Luning ,  David C. Greenlaw ,  Jonathan Fewkes

Inventor： Scott D. Luning ,  David C. Greenlaw ,  Jonathan Fewkes

IPC: H01L21/265 ,  H01L29/10 ,  H01L21/336

CPC classification number: H01L21/2652 ,  H01L29/105

Abstract: A method of manufacturing a semiconductor device with a steep retrograde profile. The threshold voltage adjust dopant layer and the punchthrough prevent dopant layer are formed in the substrate. All surface capping layers are removed from the active device regions and, the semiconductor device is placed in a chamber and a high vacuum is established after which an inert atmosphere is introduced into the chamber. The anneal to repair the damage to the lattice and to activate the dopant ions in the dopant layers is done in the inert atmosphere with the surface of the substrate maintained clean, that is, free from a capping oxide or other layer formed on the surface of the substrate.

Abstract translation: 制造具有陡峭逆行曲线的半导体器件的方法。 在衬底中形成阈值电压调整掺杂剂层和穿通防止掺杂剂层。 将所有表面覆盖层从有源器件区域中移除，并将半导体器件放置在腔室中，并建立高真空，之后将惰性气体引入腔室。 修复对晶格的损伤并激活掺杂剂层中的掺杂剂离子的退火在惰性气氛中进行，其中衬底的表面保持清洁，即，没有形成在表面上的封盖氧化物或其它层 底物。

公开(公告)号：US5795823A

公开(公告)日：1998-08-18

申请号：US752807

申请日：1996-11-20

Applicant: Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

Inventor： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L21/441

CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1036 ,  H01L2924/0002

Abstract: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings. The sidewalls serve as self aligned mask for etching via openings. The conformal material is either a conductive material which is left in place after the via openings are formed or an insulating material which is removed. In the former, the partially filled conductive line openings are filled with additional conductive material along with the via, which is either the same or different conductive material. In the latter, the conductive line openings and vias are filled with the same conductive material.

Abstract translation: 一种用于集成电路和用于半导体器件的衬底载体的绝缘体分隔开的导线的连接通孔和通孔的方法，其中使用双镶嵌仅具有一个用于形成导电线和通孔的掩​​模图案。 导电线的掩模图案包含​​在绝缘材料中要形成通孔开口的横向扩大区域。 在产生具有横向扩大区域的导电线路开口之后，开口用适形材料填充，其保护材料的蚀刻选择性基本上小于绝缘材料对用于蚀刻绝缘材料的附魔的蚀刻选择性，并且其蚀刻选择性基本上大于 绝缘材料到其附魔。 保形材料被各向异性地蚀刻以在扩大区域中形成侧壁并且移除侧壁之间的材料，而留下留在导电线开口部分中的材料。 侧壁用作通过开口蚀刻的自对准掩模。 保形材料是导电材料，其在形成通孔开口之后留在适当位置或者被去除的绝缘材料。 在前者中，部分填充的导电线路开口与另外的导电材料一起填充，该通孔是相同或不同的导电材料。 在后者中，导电线路开口和通孔用相同的导电材料填充。

公开(公告)号：US5705430A

公开(公告)日：1998-01-06

申请号：US486777

申请日：1995-06-07

Applicant: Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

Inventor： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76808 ,  H01L2221/1031

Abstract: A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a sacrificial via fill. A first layer of insulating material is formed with via openings. The openings are filled with a sacrificial removable material. A second layer of insulating material is deposed on the first layer. In one embodiment, the etch selectivity to the etchant of the second layer is essentially the same as the sacrificial via fill and, preferably, is substantially higher than second layer. Using a conductive line pattern aligned with the via openings, conductive line openings are etched in the second insulating layer and, during etching, the sacrificial fill is removed from the via openings. In a second embodiment, the sacrificial material is not etchable by the etchant for forming the conductive line openings and, after formation of the conductive line openings, the sacrificial material is removed with an etchant to which the first insulating layer is resistive or less selective. A conductive material now is deposited in the conductive line and via openings.

Abstract translation: 一种双镶嵌方法，用于制造用于集成电路的绝缘体分隔开的导电线路的互连电平和用于半导体器件的衬底载体的通孔，其使用牺牲通孔填充物。 第一层绝缘材料形成有通孔。 开口填充有牺牲可移除材料。 在第一层上放置第二层绝缘材料。 在一个实施例中，对第二层的蚀刻剂的蚀刻选择性基本上与牺牲通孔填充相同，并且优选地基本上高于第二层。 使用与通孔开口对准的导电线图案，在第二绝缘层中蚀刻导电线开口，并且在蚀刻期间，将牺牲填充物从通孔开口移除。 在第二实施例中，牺牲材料不可蚀刻用于形成导电线路开口的蚀刻剂，并且在形成导电线路开口之后，用第一绝缘层具有电阻或较小选择性的蚀刻剂去除牺牲材料。 导电材料现在沉积在导电线和通孔中。

公开(公告)号：US5691238A

公开(公告)日：1997-11-25

申请号：US478321

申请日：1995-06-07

Applicant: Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

Inventor： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/44

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76877 ,  H01L21/76885 ,  H01L2924/0002

Abstract: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer. In addition, a triple damascene layer is formed by starting with an insulating layer about one-third thicker than normal and by combining the standard dual damascene method with the above described method. The resulting interconnection level structure comprises conductive lines having upwardly and downwardly projecting vias.

Abstract translation: 一种制造导线的互连电平的方法，以及用于集成电路的绝缘和用于半导体器件的衬底载体分离的通孔的方法，其使用反向镶嵌来形成导电线和通孔。 首先使用导电线图案来完全蚀刻该层以形成导电线开口。 开口完全被导电材料填充并平坦化，使得导电材料和绝缘层的表面是共面的。 通孔图案垂直于导电线对齐，并且导电材料被除了通孔图案覆盖的区域之外的一半蚀刻通过导电线。 由此在导线的上部形成的开口用绝缘材料填充，以完成与绝缘层的下部中的导电线和层的上部中的向上突出的通孔的双镶嵌互连水平。 此外，通过从绝对层开始比正常厚约三分之一的厚度并通过将标准双镶嵌方法与上述方法组合来形成三镶嵌层。 所产生的互连级联结构包括具有向上和向下突出的通孔的导线。