利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

371 条记录 (耗时 0.034 秒)

    Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides
    42.
    发明授权
    Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides 有权
    具有超薄SOI层和掩埋氧化物的绝缘体上半导体（SOI）衬底

    公开(公告)号：US09059245B2

    公开(公告)日：2015-06-16

    申请号：US13483781

    申请日：2012-05-30

    申请人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    发明人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76243

    摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.

    摘要翻译： 提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。 使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。 氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。 在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

    SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES WITH ULTRA-THIN SOI LAYERS AND BURIED OXIDES
    43.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES WITH ULTRA-THIN SOI LAYERS AND BURIED OXIDES 有权
    半导体绝缘体（SOI）衬底，具有超薄SOI层和铜氧化物

    公开(公告)号：US20130320483A1

    公开(公告)日：2013-12-05

    申请号：US13483781

    申请日：2012-05-30

    申请人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    发明人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    IPC分类号： H01L21/762 ,  H01L29/02

    CPC分类号： H01L21/76243

    摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.

    摘要翻译： 提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。 使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。 氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。 在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

    Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets
    44.
    发明申请
    Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets 审中-公开
    具有无门侧壁的翅片结构，用于多栅极Mosfets

    公开(公告)号：US20130196488A1

    公开(公告)日：2013-08-01

    申请号：US13605085

    申请日：2012-09-06

    申请人： Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

    发明人： Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

    IPC分类号： H01L21/20

    CPC分类号： H01L29/785 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/02639 ,  H01L29/66795

    摘要： Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (ΔEc) ranging from 0.05-0.6 eV; patterning an epitaxy mask on the semi-insulating layer, wherein the epitaxy mask has a reverse image of a desired pattern of the fin; performing a selective epitaxial growth within the epitaxy mask; and removing the epitaxy mask such that the fin remains on the semi-insulating layer. The semi-insulating layer comprises, for example, a III-V semiconductor material and optionally further comprises a Si δ-doping layer to supply electron carriers to the III-V channel.

    摘要翻译： 提供了改进的鳍场效应晶体管（FinFET），以及用于形成FinFET鳍片的改进技术。 通过在绝缘体上形成半绝缘层，形成范围从0.05-0.6eV的足够大的导带偏移（DeltaEc）形成FinFET鳍; 在所述半绝缘层上构图外延掩模，其中所述外延掩模具有鳍的期望图案的反向图像; 在外延掩模内进行选择性外延生长; 并移除外延掩模，使得翅片保留在半绝缘层上。 半绝缘层包括例如III-V族半导体材料，并且任选地还包括用于向III-V沟道提供电子载流子的Si-δ掺杂层。

    Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets
    45.
    发明申请
    Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets 审中-公开
    具有无门侧壁的翅片结构，用于多栅极Mosfets

    公开(公告)号：US20130193482A1

    公开(公告)日：2013-08-01

    申请号：US13359849

    申请日：2012-01-27

    申请人： Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

    发明人： Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

    IPC分类号： H01L29/78 ,  H01L21/20

    CPC分类号： H01L29/785 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/02639 ,  H01L29/66795

    摘要： Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (ΔEe) ranging from 0.05-0.6 eV; patterning an epitaxy mask on the semi-insulating layer, wherein the epitaxy mask has a reverse image of a desired pattern of the fin; performing a selective epitaxial growth within the epitaxy mask; and removing the epitaxy mask such that the fin remains on the semi-insulating layer. The semi-insulating layer comprises, for example, a III-V semiconductor material and optionally further comprises a Si δ-doping layer to supply electron carriers to the III-V channel.

    摘要翻译： 提供了改进的鳍场效应晶体管（FinFET），以及用于形成FinFET鳍片的改进技术。 通过在绝缘体上形成半导体带偏移（DeltaEe）为0.05-0.6eV的半绝缘层，形成FinFET的鳍; 在所述半绝缘层上构图外延掩模，其中所述外延掩模具有鳍的期望图案的反向图像; 在外延掩模内进行选择性外延生长; 并移除外延掩模，使得翅片保留在半绝缘层上。 半绝缘层包括例如III-V族半导体材料，并且任选地还包括用于向III-V沟道提供电子载流子的Si-δ掺杂层。

    Semiconductor Substrates Using Bandgap Material Between III-V Channel Material and Insulator Layer
    46.
    发明申请
    Semiconductor Substrates Using Bandgap Material Between III-V Channel Material and Insulator Layer 有权
    在III-V通道材料和绝缘层之间使用带隙材料的半导体衬底

    公开(公告)号：US20130193441A1

    公开(公告)日：2013-08-01

    申请号：US13361004

    申请日：2012-01-30

    申请人： Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

    发明人： Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

    IPC分类号： H01L29/20 ,  H01L21/20

    CPC分类号： H01L27/12 ,  H01L29/1025 ,  H01L29/7781

    摘要： Improved semiconductor substrates are provided that employ a wide bandgap material between the channel and the insulator. A semiconductor substrate comprises a channel layer comprised of a III-V material; an insulator layer; and a wide bandgap material between the channel layer and the insulator layer, wherein a conduction band offset (ΔEc) between the channel layer and the wide bandgap material is between 0.05 eV and 0.8 eV. The channel layer can be comprised of, for example, In1-xGaxAs or In1-xGaxSb, with x varying from 0 to 1. The wide bandgap material can be comprised of, for example, In1-yAlyAs, In1-yAlyP, Al1-yGayAs or In1-yGayP, with y varying from 0 to 1.

    摘要翻译： 提供了改进的半导体衬底，其在通道和绝缘体之间采用宽带隙材料。 半导体衬底包括由III-V材料构成的沟道层; 绝缘体层; 以及在沟道层和绝缘体层之间的宽带隙材料，其中沟道层和宽带隙材料之间的导带偏移（DeltaEc）在0.05eV和0.8eV之间。 沟道层可以由例如In1-xGaxAs或In1-xGaxSb组成，x的变化范围为0到1.宽带隙材料可以由例如In1-yAlyAs，In1-yAlyP，Al1-yGayAs 或In1-yGayP，y从0变化到1。