Compliant passivated edge seal for low-k interconnect structures
    41.
    发明授权
    Compliant passivated edge seal for low-k interconnect structures 有权
    符合低k互连结构的钝化边缘密封

    公开(公告)号:US07273770B2

    公开(公告)日:2007-09-25

    申请号:US11464959

    申请日:2006-08-16

    摘要: A structure for a chip or chip package is disclosed, with final passivation and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in the final passivation region, with strain relief from the decoupling region and compliant leads therein, so that on-chip interconnect levels do not feel these external packaging or other stresses. This structure is particularly preferred for on-chip interconnects consisting of Cu and low-k dielectric, the latter having inferior mechanical properties relative to SiO2. The decoupled region extends over all chips on the wafer. It may also extend into the edgeseal or dicing channel region so as to allow chip dicing and retention of this mechanical decoupling all around every chip on the wafer.

    摘要翻译: 公开了一种用于芯片或芯片封装的结构,其具有机械去耦合但电耦合到多层片上互连的最终钝化和终端冶金。 这种去耦允许芯片在最终钝化区域中经受包装应力,在去耦区域和柔性引线处具有应变消除,使得片上互连电平不会感受到这些外部封装或其他应力。 对于由Cu和低k电介质组成的片上互连,该结构特别优选,后者相对于SiO 2具有差的机械性能。 去耦区延伸在晶片上的所有芯片上。 它也可以延伸到edgeseal或切割通道区域,以便允许在晶片上的每个芯片周围进行芯片切割和保持这种机械解耦。

    Post-fuse blow corrosion prevention structure for copper fuses
    48.
    发明授权
    Post-fuse blow corrosion prevention structure for copper fuses 有权
    铜熔丝保险丝熔断防腐结构

    公开(公告)号:US06498385B1

    公开(公告)日:2002-12-24

    申请号:US09388314

    申请日:1999-09-01

    IPC分类号: H01L2900

    摘要: A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications. The resistor element has low capacitance, low skin effect, high linearity, a high melting temperature, and a high critical current to failure. The resistor structure can be formed on the walls of a dielectric trough. The structure can be applied to circuit applications such as an ESD network, an RC-coupled MOSFET, a resistor ballasted MOSFET and others. The resistors can be in series with the MOSFET or other structures.

    摘要翻译: 公开了一种制造半导体耐腐蚀金属熔丝线的结构和方法,其包括也可以用作电阻器的耐火衬垫。 使用镶嵌工艺完成制作。 金属结构可以形成在包括包括第一层和第二层的第一部分的半导体衬底上,第一层具有比第二层更高的电阻率,第二层具有与第一层接触的水平和垂直表面 在第一部分中,以及第二部分,其联接到第一部分,第二部分由第一层组成,第一层不与第二部分中的第二层的水平和垂直表面接触。 金属结构可用作耐腐蚀保险丝。 金属结构也可以用作电阻元件。高耐压电阻器结构允许在混合电压,混合信号和模拟/数字应用中使用。 电阻元件具有低电容,低效果,高线性度,高熔点温度和高临界电流故障。 电阻器结构可以形成在电介质槽的壁上。 该结构可以应用于诸如ESD网络,RC耦合MOSFET,电阻器镇流MOSFET等电路应用。 电阻可以与MOSFET或其他结构串联。