公开(公告)号：US20100073094A1

公开(公告)日：2010-03-25

申请号：US12234114

申请日：2008-09-19

申请人： Tim Tri Hoang ,  Wilson Wong ,  Sergey Shumarayev

发明人： Tim Tri Hoang ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03L7/085

CPC分类号： H03L7/099 ,  H03L7/18

摘要： A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.

摘要翻译： 电路包括相位检测电路，时钟信号发生电路，第一分频器和第二分频器。 相位检测电路将输入时钟信号与反馈信号进行比较以产生控制信号。 时钟信号产生电路响应于控制信号产生周期性输出信号。 第一分频器将周期性输出信号的频率除以第一值，以产生第一分频信号。 第二分频器将周期性输出信号的频率除以第二值，以产生第二分频信号。 在不同的时间间隔期间，第一和第二分频信号作为反馈信号被路由到相位检测电路。

公开(公告)号：US20090122939A1

公开(公告)日：2009-05-14

申请号：US11329197

申请日：2006-01-09

申请人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong ,  Rakesh H. Patel

发明人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong ,  Rakesh H. Patel

IPC分类号： H04L7/00

CPC分类号： H03L7/087 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/10 ,  H04L7/0004 ,  H04L7/033

摘要： Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.

摘要翻译： 宽范围和动态可重新编程的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。 为了支持广泛的数据速率，CDR架构包括多个操作参数。 这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。 可以在不关闭电路或PLD的情况下动态重新编程参数。 这允许CDR电路在各种标准和协议之间进行即时切换。

公开(公告)号：US09246715B1

公开(公告)日：2016-01-26

申请号：US12432136

申请日：2009-04-29

申请人： Allen Chan ,  Wilson Wong ,  Tim Tri Hoang

发明人： Allen Chan ,  Wilson Wong ,  Tim Tri Hoang

IPC分类号： H03K19/094 ,  H04L25/02 ,  H03K19/003

CPC分类号： H04L25/0272 ,  H03K19/00315 ,  H03K19/00361

摘要： A pre-emphasis circuitry that includes (1) a pre-emphasis voltage variation compensation (PVVC) engine having a transition detection circuit and (2) a compensation driver coupled to the PVVC engine is described. In one embodiment, the compensation driver reduces data dependent voltage variations in pre-emphasis provided by the pre-emphasis circuitry. In one embodiment, in response to a predetermined data pattern detected by the PVVC engine, the compensation driver provides an additional boost to performance critical capacitive nodes of the pre-emphasis circuitry. The additional boost causes the performance critical capacitive nodes to charge or discharge more rapidly. In one embodiment, the PVVC engine further includes a digital finite impulse response (FIR) filter coupled to the transition detection circuit. Also, in one embodiment, the PVVC engine further includes an FIR delay circuit coupled to the digital FIR filter and a synchronizer circuit coupled to the digital FIR filter and the FIR delay circuit, where the FIR delay circuit introduces latency to match-delay produced by the transition detection circuit and the synchronizer circuit synchronizes data to be sent to the main driver, the pre-emphasis driver, and the compensation driver.

摘要翻译： 一种预加重电路，其包括（1）具有转移检测电路的预加重电压变化补偿（PVVC）引擎和（2）耦合到PVVC引擎的补偿驱动器。 在一个实施例中，补偿驱动器减少由预加重电路提供的预加重中的数据相关电压变化。 在一个实施例中，响应于由PVVC引擎检测到的预定数据模式，补偿驱动器为预加重电路的性能关键电容性节点提供额外的提升。 额外的升压会导致性能关键的电容性节点更快地充电或放电。 在一个实施例中，PVVC引擎还包括耦合到转换检测电路的数字有限脉冲响应（FIR）滤波器。 此外，在一个实施例中，PVVC引擎还包括耦合到数字FIR滤波器的FIR延迟电路和耦合到数字FIR滤波器和FIR延迟电路的同步器电路，其中FIR延迟电路将等待时间延迟到由 转换检测电路和同步器电路将要发送到主驱动器，预加重驱动器和补偿驱动器的数据同步。

公开(公告)号：US08416898B1

公开(公告)日：2013-04-09

申请号：US12483151

申请日：2009-06-11

申请人： Mei Luo ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

发明人： Mei Luo ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

IPC分类号： H04B1/10

CPC分类号： H04L25/03057 ,  H04L2025/03592

摘要： A circuit includes a receiver circuit, a decision feedback equalizer circuit, and a control loop circuit. The receiver circuit receives a data signal and generates an input signal in response to the data signal. The decision feedback equalizer circuit includes a tap driver and a first current source coupled to the tap driver. The tap driver drives the input signal based on a tap weight. The control loop circuit varies a current through the first current source based on variations in the input signal to reduce changes in the tap weight that are caused by the variations in the input signal.

摘要翻译： 电路包括接收器电路，判决反馈均衡器电路和控制回路电路。 接收器电路接收数据信号并响应于数据信号产生输入信号。 判决反馈均衡器电路包括抽头驱动器和耦合到抽头驱动器的第一电流源。 抽头驱动器根据抽头重量驱动输入信号。 控制回路电路基于输入信号的变化改变通过第一电流源的电流，以减少由输入信号的变化引起的抽头重量的变化。

公开(公告)号：US08811555B2

公开(公告)日：2014-08-19

申请号：US12700433

申请日：2010-02-04

申请人： Kazi Asaduzzaman ,  Tim Tri Hoang ,  Tin H. Lai ,  Shou-Po Shih ,  Sergey Shumarayev

发明人： Kazi Asaduzzaman ,  Tim Tri Hoang ,  Tin H. Lai ,  Shou-Po Shih ,  Sergey Shumarayev

IPC分类号： H04L7/00 ,  H03L7/081 ,  H04L7/033 ,  H03L7/08

CPC分类号： H03L7/08 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/0898 ,  H03L7/099 ,  H03L7/183 ,  H04L7/0337

摘要： An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).

摘要翻译： 集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。 由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。 响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。

公开(公告)号：US07619451B1

公开(公告)日：2009-11-17

申请号：US11670971

申请日：2007-02-03

申请人： Tim Tri Hoang ,  Sergey Shumarayev ,  Kazi Asaduzzaman ,  Wanli Chang ,  Mian Z. Smith ,  Kang-Wei Lai ,  Leon Zheng

发明人： Tim Tri Hoang ,  Sergey Shumarayev ,  Kazi Asaduzzaman ,  Wanli Chang ,  Mian Z. Smith ,  Kang-Wei Lai ,  Leon Zheng

IPC分类号： H03L7/06

CPC分类号： H03L7/0995 ,  G06F1/12 ,  H03L7/081 ,  H03L7/0812

摘要： Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an input pin and an output pin. Other circuit elements coupled in the feedback loop of a locked circuit can compensate for the delay between an input pin and a destination circuit element. Still other circuit elements coupled in an input reference path of a locked circuit preserve a timing relationship between input clock and input data signals. A clock signal and a data signal received at a destination circuit element have the same phase and timing relationship that exists between the input clock and input data signals at input pins.

摘要翻译： 提供了用于补偿由集成电路上的锁相环和延迟锁定环路产生的时钟信号中的相位和定时延迟的技术。 耦合在锁定电路的反馈回路中的电路元件可以补偿输入引脚和输出引脚之间的定时和相位延迟。 耦合在锁定电路的反馈环路中的其它电路元件可以补偿输入引脚和目的地电路元件之间的延迟。 耦合在锁定电路的输入参考路径中的其他电路元件保留输入时钟和输入数据信号之间的定时关系。 在目的地电路元件处接收的时钟信号和数据信号在输入引脚的输入时钟和输入数据信号之间具有相同的相位和定时关系。

公开(公告)号：US20110188621A1

公开(公告)日：2011-08-04

申请号：US12700433

申请日：2010-02-04

申请人： Kazi Asaduzzaman ,  Tim Tri Hoang ,  Tin H. Lai ,  Shou-Po Shih ,  Sergey Shumarayev

发明人： Kazi Asaduzzaman ,  Tim Tri Hoang ,  Tin H. Lai ,  Shou-Po Shih ,  Sergey Shumarayev

IPC分类号： H04L7/00

CPC分类号： H03L7/08 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/0898 ,  H03L7/099 ,  H03L7/183 ,  H04L7/0337

摘要： An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.

摘要翻译： 集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。 由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。 响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。 这可以帮助IC支持采用自动速度协商的通信协议。

公开(公告)号：US07812659B1

公开(公告)日：2010-10-12

申请号：US11432420

申请日：2006-05-10

申请人： Sergey Shumarayev ,  Rakesh H Patel ,  William W Bereza ,  Tim Tri Hoang ,  Thungoc Tran

发明人： Sergey Shumarayev ,  Rakesh H Patel ,  William W Bereza ,  Tim Tri Hoang ,  Thungoc Tran

IPC分类号： G06F1/04 ,  H04L7/00

CPC分类号： H03L7/22 ,  G06F1/06

摘要： A programmable logic device (“PLD”) or the like has a plurality of data transmitter channels. Certain circuitry is shared by the channels. The shared circuitry includes at least one phase-locked loop (“PLL”) circuit for producing a primary clock signal, and global frequency divider circuitry for producing at least one global secondary clock signal based on the primary signal. The primary and global secondary signal(s) are distributed to the channels. Each of the channels includes local frequency divider circuitry for producing at least one local secondary clock signal based on the primary signal. Each channel also includes selection circuitry for selecting either the global or local secondary signal(s) for use by clock utilization circuitry of the channel. The clock utilization circuitry may include serializer circuitry for converting data from parallel to serial form.

摘要翻译： 可编程逻辑器件（“PLD”）等具有多个数据发送器通道。 某些电路由通道共享。 共享电路包括用于产生主时钟信号的至少一个锁相环（“PLL”）电路和用于基于主信号产生至少一个全局辅助时钟信号的全局分频器电路。 主要和全局辅助信号被分配到信道。 每个通道包括本地分频器电路，用于基于主信号产生至少一个本地辅助时钟信号。 每个通道还包括选择电路，用于选择由信道的时钟利用电路使用的全局或局部辅助信号。 时钟利用电路可以包括用于将数据从并行转换为串行形式的串行化器电路。

公开(公告)号：US20090161738A1

公开(公告)日：2009-06-25

申请号：US12283652

申请日：2008-09-15

申请人： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

发明人： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

IPC分类号： H04L7/00 ,  H04B1/38

CPC分类号： H04L25/14

摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

摘要翻译： 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

公开(公告)号：US20080246516A1

公开(公告)日：2008-10-09

申请号：US11696575

申请日：2007-04-04

申请人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wanli Chang

发明人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wanli Chang

IPC分类号： H03D13/00

CPC分类号： H03D13/004

摘要： A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals. The one or more output signals have a minimum pulse width. The phase frequency detector has a temperature sensing circuit. The phase frequency detector adjusts the minimum pulse width of the one or more output signals using the temperature sensing circuit to compensate for variations in the temperature of the phase frequency detector.

摘要翻译： 相位频率检测器将参考时钟信号与反馈时钟信号进行比较，以在一个或多个输出信号中产生脉冲。 一个或多个输出信号具有最小的脉冲宽度。 相位频率检测器具有温度检测电路。 相位频率检测器使用温度检测电路调节一个或多个输出信号的最小脉冲宽度，以补偿相位频率检测器的温度变化。