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228 条记录 (耗时 0.036 秒)

    High-performance memory interface circuit architecture
    41.
    发明授权
    High-performance memory interface circuit architecture 有权
    高性能存储器接口电路架构

    公开(公告)号：US07227395B1

    公开(公告)日：2007-06-05

    申请号：US11055125

    申请日：2005-02-09

    申请人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

    发明人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0812 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0805

    摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

    摘要翻译： 可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。 然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略 相移控制设置，以产生精细的相移控制设置。 粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

    Address control for efficient memory partition
    43.
    发明授权
    Address control for efficient memory partition 有权
    地址控制用于高效的内存分区

    公开(公告)号：US07057962B1

    公开(公告)日：2006-06-06

    申请号：US10806638

    申请日：2004-03-22

    申请人： Johnson Tan ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Joseph Huang

    发明人： Johnson Tan ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Joseph Huang

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1075

    摘要： A memory cell of a programmable device includes a memory partitioning circuit to partition a multiple port memory device into one or more single port memory partitions. The memory partitioning circuit prevents cross addressing by setting the value of one or more address lines of each memory port to a fixed value. The memory partitioning circuit holds address lines at their required values during the programmable device's normal, clear, and reset modes of operation. The behavior of the memory partitioning circuit is set by a portion of a device configuration used to configure the programmable device. The memory partitioning circuit is connected between a memory cell's address register and row or column decoders used to access the multiple port memory device. The memory partitioning circuit can also perform bit-wise inversion operations on portions of the memory addresses.

    摘要翻译： 可编程设备的存储单元包括用于将多端口存储器设备分割成一个或多个单端口存储器分区的存储器分配电路。 存储器分配电路通过将每个存储器端口的一个或多个地址线的值设置为固定值来防止交叉寻址。 存储器分配电路在可编程器件的正常，清零和复位操作模式期间将地址线保持在其所需的值。 存储器分配电路的行为由用于配置可编程器件的器件配置的一部分来设置。 存储器分配电路连接在存储单元的地址寄存器和用于访问多端口存储器件的行或列解码器之间。 存储器分配电路还可以对存储器地址的部分执行逐位反转操作。

    DQS postamble filtering
    44.
    发明授权
    DQS postamble filtering 失效
    DQS后同步码过滤

    公开(公告)号：US07031222B1

    公开(公告)日：2006-04-18

    申请号：US11046007

    申请日：2005-01-28

    申请人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

    发明人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

    IPC分类号： G11C8/00

    CPC分类号： H03K5/135 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  H03M9/00

    摘要： Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.

    摘要翻译： 用于在高速数据接口处过滤信号的电路，方法和装置。 一个示例性实施例被特别地配置为在由双数据速率存储器接口接收的数据突发结束时对时钟信号进行滤波。 时钟输入端口与输入单元连接或断开。 当接收到数据脉冲串时，时钟输入端口连接到输入单元。 当数据突发结束时，时钟输入端口与输入单元断开连接。 在具体实施例中，接收到指示数据脉冲串即将开始并且时钟输入端口连接到输入单元的信号。 该信号随后改变指示正在接收最后一个数据位的状态。 当接收到与最后一个数据位相对应的最后一个时钟沿时，时钟输入端口与输入单元断开。

    Programmable I/O element circuit for high speed logic devices
    46.
    发明申请
    Programmable I/O element circuit for high speed logic devices 有权
    用于高速逻辑器件的可编程I / O元件电路

    公开(公告)号：US20050162187A1

    公开(公告)日：2005-07-28

    申请号：US11025774

    申请日：2004-12-29

    申请人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

    发明人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

    IPC分类号： C07K14/47 ,  C07K16/28 ,  H03K19/177

    CPC分类号： C07K16/28 ,  A61K2039/505 ,  C07K14/47

    摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

    摘要翻译： 用于逻辑阵列的I / O端子的可编程I / O元件适用于根据双速数据速率和零总线周转等高速I / O模式进行工作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。 另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。 对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块为输出缓冲器的选通输入提供使能信号。 可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

    Schmitt trigger circuit with adjustable trip point voltages
    47.
    发明授权
    Schmitt trigger circuit with adjustable trip point voltages 有权
    施密特触发电路具有可调跳闸点电压

    公开(公告)号：US06870413B1

    公开(公告)日：2005-03-22

    申请号：US10017933

    申请日：2001-12-14

    申请人： Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Yan Chong ,  Xiaobao Wang ,  Philip Pan ,  Gopinath Rangan ,  In Whan Kim

    发明人： Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Yan Chong ,  Xiaobao Wang ,  Philip Pan ,  Gopinath Rangan ,  In Whan Kim

    IPC分类号： H03K3/3565 ,  H03K3/012

    CPC分类号： H03K3/3565

    摘要： A Schmitt trigger circuit has an adjustable hysteresis characteristic by providing a plurality of feedback circuits that differently affect at least one, and preferably both, of the circuit's upper trip point level and lower trip point level. The upper trip point level can be adjusted by selecting a desired feedback circuit from a first set of feedback circuits, and/or the lower trip point level can be adjusted by selecting a desired feedback circuit from a second set of feedback circuits. Feedback circuit selection is achieved by one or more control signals that may be programmable. The hysteresis characteristic can be adjusted to meet desired noise margin, delay, and input recognition criteria at different VCC levels. The Schmitt trigger circuit may be a CMOS Schmitt trigger with two input stage NMOS, two input stage PMOS transistors, a first set of NMOS feedback circuits, and a second set of PMOS feedback circuits.

    摘要翻译： 施密特触发电路具有可调滞后特性，通过提供多个反馈电路，其不同地影响电路的上跳点电平和较低跳变点电平的至少一个，优选两者。 可以通过从第一组反馈电路中选择所需的反馈电路来调整上跳点电平，和/或可以通过从第二组反馈电路中选择所需的反馈电路来调整下跳变点电平。 反馈电路选择由一个或多个可编程的控制信号来实现。 可以调节滞后特性，以满足不同VCC电平下的所需噪声容限，延迟和输入识别准则。 施密特触发电路可以是具有两个输入级NMOS，两个输入级PMOS晶体管，第一组NMOS反馈电路组和第二组PMOS反馈电路的CMOS施密特触发器。

    Dual-port SRAM in a programmable logic device
    49.
    发明授权
    Dual-port SRAM in a programmable logic device 有权
    可编程逻辑器件中的双端口SRAM

    公开(公告)号：US06661733B1

    公开(公告)日：2003-12-09

    申请号：US09883087

    申请日：2001-06-15

    申请人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong

    发明人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong

    IPC分类号： G11C800

    CPC分类号： H03K19/1776 ,  G11C8/16

    摘要： Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.

    摘要翻译： 可编程逻辑器件中双端口SRAM的方法和装置。 一个实施例提供了包括双端口存储器的可编程逻辑集成电路。 存储器包括多个存储器存储单元，并且每个存储器存储单元具有具有第一节点和第二节点的存储单元，连接在第一数据线和存储器单元的第一节点之间的第一系列器件，以及 连接在第二数据线和存储器单元的第二节点之间的第二系列器件。 读单元连接到存储单元的第二节点。 字线连接到第一系列设备中的第一设备，第二系列设备中的第二设备和读取单元。

    Circuit design technique for DQS enable/disable calibration
    50.
    发明授权
    Circuit design technique for DQS enable/disable calibration 有权
    DQS的电路设计技术启用/禁用校准

    公开(公告)号：US08787097B1

    公开(公告)日：2014-07-22

    申请号：US13250155

    申请日：2011-09-30

    申请人： Yan Chong ,  Joseph Huang ,  Sean Shau-Tu Lu ,  Pradeep Nagarajan ,  Chiakang Sung

    发明人： Yan Chong ,  Joseph Huang ,  Sean Shau-Tu Lu ,  Pradeep Nagarajan ,  Chiakang Sung

    IPC分类号： G11C7/00

    CPC分类号： G06F17/5031 ,  G06F2217/84 ,  G11C7/1066

    摘要： Systems and methods are disclosed for calibrating a Data Strobe (DQS) enable/disable signal and for tracking the timing of the DQS enable/disable signal with respect to changes in voltage and temperature (VT) in order to improve the timing margin of the DQS enable/disable signal in programmable devices using Double Data Rate (DDR) memory. In an exemplary embodiment, the system includes a gating circuit, a sampling circuit, and a delay chain tracking circuit. The gating circuit receives a DQS enable signal and a input DQS signal, calibrates the DQS enable signal based on an amount of delay, and outputs the calibrated DQS signal. The sampling circuit provides the amount of delay to the gating circuit based on a sampling clock. The delay chain tracking circuit maintains the timing of the calibrated DQS enable signal over a plurality of clock cycles based on the sampling clock and a leveling clock.

    摘要翻译： 公开了用于校准数据选通（DQS）使能/禁止信号的系统和方法，并且用于跟踪DQS使能/禁止信号相对于电压和温度（VT）的变化的定时，以便改善DQS的定时裕度 使用双倍数据速率（DDR）存储器在可编程器件中启用/禁用信号。 在示例性实施例中，该系统包括门控电路，采样电路和延迟链跟踪电路。 门控电路接收DQS使能信号和输入DQS信号，根据延迟量校准DQS使能信号，并输出校准的DQS信号。 采样电路基于采样时钟向门控电路提供延迟量。 延迟链跟踪电路基于采样时钟和调平时钟在多个时钟周期上维持校准的DQS使能信号的定时。