公开(公告)号：US5747849A

公开(公告)日：1998-05-05

申请号：US669938

申请日：1996-06-25

申请人： Kenichi Kuroda ,  Kazuyoshi Shiba ,  Akinori Matsuo

发明人： Kenichi Kuroda ,  Kazuyoshi Shiba ,  Akinori Matsuo

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0491 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7883

摘要： A semiconductor substrate of a first conductivity type has formed on its main surface a floating gate through a first gate insulating film and has further formed over the floating gate a control gate through a second gate insulating film. In one of a paired source and drain and across which there is provided the floating gate insulately above the main surface of the substrate, a semiconductor region of second conductivity type having a lower impurity concentration than that of the paired source and drain is formed in a portion of the substrate overlapping the floating gate. A nonvolatile memory device thus constructed has its writing operation carried out by extracting electrons from the floating gate to the other of the paired source and drain having a semiconductor region of the second conductivity type, having a higher impurity concentration, by an F-N tunneling of electrons flowing through the first gate insulating film and its erasing operation carried out by injecting from the paired source and drain or the semiconductor substrate into the floating gate by the F-N tunneling of electrons flowing through the first gate insulating film. Data lines or source lines can be shared between memory cells adjacent to each other in a word line direction so that the memory cells can be substantially small-sized. The writing operation and the erasing operation can be carried out by the tunnel current so that the corresponding necessary high voltages can be generated by the internal circuits.

摘要翻译： 第一导电类型的半导体衬底在其主表面上通过第一栅极绝缘膜形成浮栅，并且还通过第二栅极绝缘膜在浮栅上形成控制栅极。 在成对的源极和漏极中的一个中，在衬底的主表面上绝缘地设置浮置栅极，具有比成对的源极和漏极的杂质浓度低的第二导电类型的半导体区域形成在 衬底的一部分与浮动栅极重叠。 如此构造的非易失性存储器件的写入操作是通过将电子从浮栅提取到具有具有较高杂质浓度的第二导电类型的半导体区域的成对源极和漏极中的另一个，通过电子的FN隧穿 流过第一栅极绝缘膜及其擦除操作，其通过由穿过第一栅极绝缘膜的电子的FN隧穿而从成对的源极和漏极或半导体衬底注入到浮置栅极中进行。 数据线或源极线可以在字线方向上彼此相邻的存储单元之间共享，使得存储器单元可以基本上小型化。 可以通过隧道电流进行写入操作和擦除操作，使得内部电路可以产生相应的必要的高电压。

公开(公告)号：US5550770A

公开(公告)日：1996-08-27

申请号：US458159

申请日：1995-06-02

申请人： Kenichi Kuroda

发明人： Kenichi Kuroda

IPC分类号： G11C11/22 ,  G11C14/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/0688 ,  G11C11/223 ,  G11C2207/063

摘要： There are provided a plurality of ferroelectric capacitors each of which having one of a pair of electrodes thereof connected with one terminal of a switch element which has the control terminal thereof connected with a first address selecting line. Second address selecting lines are respectively connected with the other electrodes of the ferroelectric capacitors to construct a unit memory circuit. When the switch element is turned ON by the first address selecting line, one of the second address selecting line is brought into a selecting state to feed such a voltage as to polarize the ferroelectric capacitors. The remaining address selecting lines are set to an unselect potential so that the voltage to be applied to the unselected ferroelectric capacitors coupled to the remaining address selecting lines may be about one half as high as that applied to the selected ferroelectric capacitor. When the switch element is turned ON by the first address selecting line, the second address selecting lines are fed with such an unselect potential as to reduce the voltage to be applied to the ferroelectric capacitors substantially to zero. The stress to the ferroelectric capacitors of the unit memory circuit corresponding to the unselected switch element can be reduced because no voltage is applied to the ferroelectric capacitors.

摘要翻译： 设有多个铁电电容器，每个铁电电容器的一对电极中的一个电极与开关元件的一个端子连接，开关元件的控制端与第一地址选择线相连。 第二地址选择线分别与铁电电容器的其他电极连接，构成单位存储电路。 当通过第一地址选择线将开关元件接通时，第二地址选择线中的一个进入选择状态，以馈送这样的电压以使铁电电容器极化。 剩余地址选择线被设置为未选择电位，使得耦合到剩余地址选择线的未选择的铁电电容器的电压可以是施加到所选择的铁电电容器的电压的约一半。 当通过第一地址选择线使开关元件接通时，第二地址选择线被馈送这样的非选择电位，以将施加到铁电电容器的电压基本上减小到零。 与非选择开关元件相对应的单位存储电路的铁电电容器的应力可以降低，因为不会对铁电电容器施加电压。

公开(公告)号：US5487029A

公开(公告)日：1996-01-23

申请号：US111507

申请日：1993-08-24

申请人： Kenichi Kuroda

发明人： Kenichi Kuroda

IPC分类号： G11C11/22 ,  G11C14/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/0688 ,  G11C11/223 ,  G11C2207/063

摘要： There are provided a plurality of ferroelectric capacitors each of which having one of a pair of electrodes thereof connected with one terminal of a switch element which has the control terminal thereof connected with a first address selecting line. Second address selecting lines are respectively connected with the other electrodes of the ferroelectric capacitors to construct a unit memory circuit. When the switch element is turned ON by the first address selecting line, one of the second address selecting lines is brought into a selecting state to feed such a voltage as to polarize the ferroelectric capacitors. The remaining address selecting lines are set to an unselect potential so that the voltage to be applied to the unselected ferroelectric capacitors coupled to the remaining address selecting lines may be about one half as high as that applied to the selected ferroelectric capacitor. When the switch element is turned ON by the first address selecting line, the second address selecting lines are fed with such an unselect potential as to reduce the voltage to be applied to the ferroelectric capacitors substantially to zero. The stress to the ferroelectric capacitors of the unit memory circuit corresponding to the unselected switch element can be reduced because no voltage is applied to the ferroelectric capacitors.

摘要翻译： 设有多个铁电电容器，每个铁电电容器的一对电极中的一个电极与开关元件的一个端子连接，开关元件的控制端与第一地址选择线相连。 第二地址选择线分别与铁电电容器的其他电极连接，构成单位存储电路。 当通过第一地址选择线使开关元件接通时，第二地址选择线之一进入选择状态，以馈送这样的电压以使铁电电容器极化。 剩余的地址选择线被设置为未选择电位，使得耦合到剩余地址选择线的未选择的铁电电容器的电压可以是施加到所选铁电电容器的电压的约一半。 当通过第一地址选择线使开关元件接通时，第二地址选择线被馈送这样的非选择电位，以将施加到铁电电容器的电压基本上减小到零。 与非选择开关元件相对应的单位存储电路的铁电电容器的应力可以降低，因为不会对铁电电容器施加电压。

公开(公告)号：US5444664A

公开(公告)日：1995-08-22

申请号：US274279

申请日：1994-07-13

申请人： Kenichi Kuroda ,  Kiyoshi Matsubara

发明人： Kenichi Kuroda ,  Kiyoshi Matsubara

IPC分类号： G06F15/78 ,  G06F9/24 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  G11C17/00 ,  H01L27/10 ,  G11C13/00

CPC分类号： G11C16/102 ,  G06F9/24 ,  G11C16/16 ,  G11C16/30

摘要： A microcomputer mounted on a single semiconductor chip includes a central processing unit and a nonvolatile flash memory which allows the information to be processed by the central processing unit to be re-programmed by electrical erasing and programming operations. The microcomputer is provided with a normal power supply voltage terminal and a programming power supply voltage terminal and also incorporates a power supply voltage level detection device and an internal voltage boost circuit to decide the re-programming mode for the flash memory according to the level of the voltage supplied and to select between the boost voltage and the external high voltage in performing the erasing and programming of data.

摘要翻译： 安装在单个半导体芯片上的微型计算机包括中央处理单元和非易失性闪存，其允许由中央处理单元处理的信息通过电擦除和编程操作重新编程。 微型计算机配备有正常的电源电压端子和编程电源电压端子，并且还包括电源电压电平检测装置和内部升压电路，以根据闪存的电平来决定闪存的重新编程模式 在执行数据的擦除和编程时，提供电压并在升压电压和外部高电压之间进行选择。

公开(公告)号：US5194924A

公开(公告)日：1993-03-16

申请号：US781592

申请日：1991-10-23

申请人： Kazuhiro Komori ,  Kenichi Kuroda ,  June Sugiura

发明人： Kazuhiro Komori ,  Kenichi Kuroda ,  June Sugiura

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11546

摘要： Disclosed is a semiconductor integrated circuit device which includes first field effect transistors with an LDD structure having a floating gate in memory cells and second field effect transistors with an LDD structure as elements other than memory cells, and which is used as an EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.

摘要翻译： 公开了一种半导体集成电路器件，其包括具有在存储器单元中具有浮动栅极的LDD结构的第一场效应晶体管和具有作为除了存储器单元之外的元素的LDD结构的第二场效应晶体管，并且被用作EPROM。 作为其源极或漏极区域的一部分的第一场效应晶体管的浅的低杂质浓度区域具有比作为其源极或漏极区域的一部分的第二场效应晶体管的浅的，低杂质浓度区域的杂质浓度更高的杂质浓度 。

公开(公告)号：US5182719A

公开(公告)日：1993-01-26

申请号：US598774

申请日：1990-10-18

申请人： Kenichi Kuroda ,  Akinori Matsuo

发明人： Kenichi Kuroda ,  Akinori Matsuo

IPC分类号： H01L21/8247 ,  H01L27/02 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546 ,  H01L27/0207

摘要： A method of fabricating a second semiconductor integrated circuit device includes steps of forming a first semiconductor integrated circuit device which has a microcomputer and is furnished with an EPROM; determining a program for controlling the microcomputer and to be set in the EPROM (performing an initial evaluation) while information is being written into and erased from the EPROM built in the first semiconductor integrated circuit device; and thereafter forming a second semiconductor integrated circuit device in which the EPROM of the first semiconductor integrated circuit device is replaced with a mask ROM. In replacing the EPROM with the mask ROM, the peripheral circuits required for both the EPROM and the mask ROM have their circuit arrangements held basically the same, and specific peripheral circuits for use in only the EPROM have their circuit regions left as they are as logically inactive regions.

摘要翻译： 制造第二半导体集成电路器件的方法包括以下步骤：形成具有微计算机并具有EPROM的第一半导体集成电路器件; 确定用于控制微型计算机的程序并将其设置在EPROM中（执行初始评估），同时信息被写入并从内置于第一半导体集成电路器件中的EPROM擦除; 然后形成第二半导体集成电路器件，其中第一半导体集成电路器件的EPROM被掩模ROM代替。 在使用掩模ROM替换EPROM时，EPROM和掩模ROM所需的外围电路的电路布置基本相同，仅在EPROM中使用的特定外围电路的逻辑电路区域保持不变 非活动区域。

公开(公告)号：US5098855A

公开(公告)日：1992-03-24

申请号：US479151

申请日：1990-03-28

申请人： Kazuhiro Komori ,  Kenichi Kuroda ,  June Sugiura

发明人： Kazuhiro Komori ,  Kenichi Kuroda ,  June Sugiura

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11546 ,  Y10S257/90

摘要： Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of a LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.

公开(公告)号：US4697198A

公开(公告)日：1987-09-29

申请号：US763612

申请日：1985-08-08

申请人： Kazuhiro Komori ,  Kenichi Kuroda ,  Kousuke Okuyama

发明人： Kazuhiro Komori ,  Kenichi Kuroda ,  Kousuke Okuyama

IPC分类号： H01L29/10 ,  H01L29/78

CPC分类号： H01L29/1083 ,  H01L29/1033 ,  H01L29/78 ,  Y10S438/919

摘要： Disclosed herein is a MOS-type field-effect transistor in which a semiconductor region having the same type of conductivity as the substrate and an impurity concentration higher than that of the substrate is formed under the channel so as to come at both ends thereof into contact with the source and drain regions. The semiconductor region restricts the extension of depletion layer from the source and drain regions, and restricts the short-channel effect. The junction capacity is small between the semiconductor region and the source and drain regions.

摘要翻译： 这里公开了一种MOS型场效应晶体管，其中在沟道下方形成具有与衬底相同类型的导电性并且杂质浓度高于衬底的半导体区域，以使其两端处于接触状态 与源极和漏极区域。 半导体区域限制耗尽层从源极和漏极区域的延伸，并限制短沟道效应。 在半导体区域和源极和漏极区域之间的结电容小。

公开(公告)号：US08744324B2

公开(公告)日：2014-06-03

申请号：US13175001

申请日：2011-07-01

申请人： Yoshihisa Mizumoto ,  Akihiko Kawatani ,  Takashi Marui ,  Kenichi Kuroda

发明人： Yoshihisa Mizumoto ,  Akihiko Kawatani ,  Takashi Marui ,  Kenichi Kuroda

IPC分类号： G03G15/08

CPC分类号： G03G15/0818 ,  G03G2215/0634

摘要： The semiconductive roller according to the present invention includes a roller body having an outer peripheral surface made of a crosslinked substance of a semiconductive rubber composition and exhibiting Shore A hardness of not more than 60, the semiconductive rubber composition contains a base polymer made of a mixture of (1) mixed rubber N of liquid nitrile rubber and solid nitrile rubber, (2) chloroprene rubber C, and (3) epichlorohydrin rubber E in a mass ratio (C+E)/N of 10/90 to 80/20, the ratios of the chloroprene rubber and the epichlorohydrin rubber in the total quantity of the base polymer are not less than 5 mass % and not less than 5 mass % respectively, and roller resistance at an applied voltage of 5 V is not less than 104Ω and not more than 109Ω.

摘要翻译： 根据本发明的半导电辊包括：具有由半导体橡胶组合物的交联物质制成的外周表面并且肖氏A硬度不大于60的辊体，所述半导体橡胶组合物含有由混合物制成的基础聚合物 的（1）混合橡胶N为液态丁腈橡胶和固体丁腈橡胶，（2）氯丁二烯橡胶C和（3）表氯醇橡胶E的质量比（C + E）/ N为10/90〜80/20， 氯丁橡胶和表氯醇橡胶在基础聚合物总量中的比例分别不低于5质量％且不小于5质量％，施加电压为5V时的辊电阻不小于104＆OHgr; 不超过109＆OHgr。

公开(公告)号：US07336535B2

公开(公告)日：2008-02-26

申请号：US11727693

申请日：2007-03-28

申请人： Kenichi Kuroda ,  Toshifumi Takeda ,  Hisahiro Moriuchi ,  Masaki Shirai ,  Jiroh Sakaguchi ,  Akinori Matsuo ,  Shoji Yoshida

发明人： Kenichi Kuroda ,  Toshifumi Takeda ,  Hisahiro Moriuchi ,  Masaki Shirai ,  Jiroh Sakaguchi ,  Akinori Matsuo ,  Shoji Yoshida

IPC分类号： G11C16/04

CPC分类号： H01L27/11526 ,  G11C16/0408 ,  G11C16/10 ,  G11C29/789 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11546

摘要： A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.

摘要翻译： 单层栅型结构的非易失性存储元件被布置成使得浮置栅极由与扩散层形成的控制栅极部分重叠的导电层形成，并且设置有覆盖部分的阻挡层 或浮动门的整个表面。 其特征在于的非易失性存储元件用于缺陷的冗余控制或功能的改变。