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公开(公告)号：US06949903B2
公开(公告)日：2005-09-27
申请号：US10298332
申请日：2002-11-18
摘要： When digitizing a voltage, a capacitor is charged, through an impedance, to a voltage value (Um) dependent on the voltage to be digitized. The limits of that one of a plurality of voltage ranges in which said voltage value (Um) lies, are ascertained, and the two limits of that voltage range are defined as a first limit and second limit; the voltage at the capacitor is modified to the first limit by a charge modification circuit containing an impedance, and a first time interval needed therefor is identified; the voltage at the capacitor is modified to the second limit; the voltage at the capacitor is modified from the second to the first limit via the charge modification circuit. A seond time interval needed therefor is identified. Based on values of the first time interval and second time interval, a digital value is calculated, which serves as an indication of how much the voltage value (Um) at the capacitor differs from one of said two limits.
摘要翻译： 当电压数字化时，电容器通过阻抗被充电到取决于要数字化的电压的电压值（Um）。 确定所述电压值（Um）所在的多个电压范围中的一个的极限，并将该电压范围的两个限定为第一限制和第二限制; 通过包含阻抗的电荷修改电路将电容器的电压修改为第一极限，并且确定所需的第一时间间隔; 将电容器的电压修改为第二极限; 电容器的电压经由充电修改电路从第二限制修改为第一限制。 确定需要的时间间隔。 基于第一时间间隔和第二时间间隔的值，计算数字值，其用作电容器上的电压值（Um）与所述两个限制之一不同的指示。
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公开(公告)号：US4989005A
公开(公告)日：1991-01-29
申请号：US244552
申请日：1988-09-12
CPC分类号： H03M1/0602 , H03K5/1532 , H03M1/54
摘要： An analog/digital converter includes a peak holding circuit for holding a peak voltage of input analog data and a peak time detecting circuit for detecting a point of time when the input analog data reaches a peak voltage. Also included is a constant current discharging circuit for discharging the peak voltage held in the peak holding circuit at a constant current from the peak point of time detected by the peak time detecting circuit. The converter also includes a zero time detecting circuit for detecting a zero point of time when a voltage held in the peak holding circuit is reduced to zero and a time to digital converting circuit for counting a number of pulses in a pulse line obtained by gating clock pulses during a period of time from the peak time detected by the peak detecting circuit to the zero time detected by the zero time detecting circuit, the time to digital converting including a counter to output digital data corresponding to the input analog data. A positive offset analog voltage is added to the input analog data and a digital compensator compensates the digital data obtained by the time to digital converting circuit by providing a negative offset digital value approximately corresponding to the positive offset analog voltage, more correctly, equal to a number of pulses in a pulse line passing through a clock gate of the time-to-digital converting circuit for a period of time during which the input analog data has a value equal to zero.
摘要翻译： 模拟/数字转换器包括用于保持输入模拟数据的峰值电压的峰值保持电路和用于检测输入模拟数据达到峰值电压的时间点的峰值时间检测电路。 还包括一个恒定电流放电电路，用于从峰值时间检测电路检测到的峰值时间点以恒定电流放电保持在峰值保持电路中的峰值电压。 该转换器还包括一个零时间检测电路，用于在保持在峰值保持电路中的电压降至零时检测零点时间;以及时间到数字转换电路，用于对通过选通时钟获得的脉冲线中的脉冲数进行计数 在从由峰值检测电路检测到的峰值时间到由零时间检测电路检测到的零时间的时间段内的脉冲，包括计数器的数字转换时间对应于输入的模拟数据的输出数字数据。 正偏移模拟电压被添加到输入模拟数据，数字补偿器通过提供大致对应于正偏移模拟电压的负偏移数字值来补偿由数字转换电路获得的数字数据，更正确地等于a 通过时间数字转换电路的时钟门的脉冲线中的脉冲数，其中输入模拟数据具有等于零的时间段。
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公开(公告)号：US09847790B2
公开(公告)日：2017-12-19
申请号：US15506234
申请日：2015-08-27
申请人： MEDIATEK INC.
发明人： Chun-Cheng Liu
摘要： A hybrid analog-to-digital converter (ADC) includes a plurality of analog-to-digital conversion circuits and a combining circuit. The analog-to-digital conversion circuits generate a plurality of partial digital outputs for a same analog input, respectively, wherein the analog-to-digital conversion circuits include a digital slope ADC used to perform signal quantization in a time domain. The combining circuit combines the partial digital outputs generated from the analog-to-digital conversion circuits to generate a final digital output of the analog input.
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公开(公告)号：US09071270B2
公开(公告)日：2015-06-30
申请号：US13906590
申请日：2013-05-31
发明人： Tracy Johancsik , Ryan James Kier , Yusuf Haque
CPC分类号： H03M1/54 , H03M1/1061 , H03M1/1215 , H03M1/1245
摘要： A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.
摘要翻译： 时间交织的模数转换器（ADC）包括一组时间多路复用子ADC电路，每个子ADC电路包括采样和保持电路。 每个采样和保持电路包括一个自举电路，用于在开关的输入端和开关的栅极端之间保持恒定的电压电平，用于在轨道模式和保持模式之间切换的开关以及电容器组相关联 其中自举电路使得电容器组的设置影响电压电平。
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公开(公告)号：US08969771B2
公开(公告)日：2015-03-03
申请号：US13504471
申请日：2010-12-20
申请人： Yasuji Ikeda , Hiroki Hiyama , Kazuo Yamazaki
发明人： Yasuji Ikeda , Hiroki Hiyama , Kazuo Yamazaki
IPC分类号： H01L27/146 , H04N5/378 , H03M1/06 , H03M1/16 , H03M1/54
CPC分类号： H04N5/378 , H03M1/0607 , H03M1/162 , H03M1/54
摘要： An imaging system includes an A/D converter including a holding unit holding a pixel signal as a voltage level, a comparator comparing the voltage level held with a reference level, a circuit capable of changing the voltage level so as to approach the reference level at first and second rates, wherein the voltage level is changed at the first rate to determine higher bits in accordance with inversion of a relationship between the reference level and the voltage level, after that, the voltage level is changed at the second rate to determine lower bits in accordance with inversion of the relationship between the reference level and the voltage level, and an adjusting unit which adjusts the voltage level during a period until the voltage level is changed at the second rate after determination of the higher bits so that the lower bits and the voltage level hold a linear relationship.
摘要翻译： 一种成像系统包括：A / D转换器，其包括保持像素信号作为电压电平的保持单元，将保持的电压电平与基准电平进行比较的比较器，能够改变电压电平以便接近基准电平的电路 第一和第二速率，其中电压电平以第一速率改变以根据参考电平和电压电平之间的关系的反转来确定较高位，之后，以第二速率改变电压电平以确定较低的电平 根据参考电平和电压电平之间的关系的反转，调整单元，以及调整单元，其在确定较高位之后调整电压电平，直到电压电平以第二速率改变，使得较低位 并且电压电平保持线性关系。
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公开(公告)号：US20130265182A1
公开(公告)日：2013-10-10
申请号：US13906590
申请日：2013-05-31
发明人： Tracy Johancsik , Ryan James Kier , Yusuf Haque
IPC分类号： H03M1/54
CPC分类号： H03M1/54 , H03M1/1061 , H03M1/1215 , H03M1/1245
摘要： A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.
摘要翻译： 时间交织的模数转换器（ADC）包括一组时间多路复用子ADC电路，每个子ADC电路包括采样和保持电路。 每个采样和保持电路包括一个自举电路，用于在开关的输入端和开关的栅极端之间保持恒定的电压电平，用于在轨道模式和保持模式之间切换的开关以及电容器组相关联 其中自举电路使得电容器组的设置影响电压电平。
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公开(公告)号：US08522087B2
公开(公告)日：2013-08-27
申请号：US13019873
申请日：2011-02-02
IPC分类号： G06K5/04
CPC分类号： H04L7/0331 , G04F10/005 , G06F11/0793 , G11C11/4076 , G11C11/5642 , G11C29/02 , G11C29/12015 , G11C2211/5644 , H03M1/207 , H03M1/54
摘要： A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output.
摘要翻译： 计数器配置与延迟配置协同工作，使得计数器配置基于给定的时钟速度和给定的时钟间隔对输入间隔进行计数，而延迟配置提供的增强数据输出大于由 给定时钟速度。 计数器配置响应于时钟间隔中的选定边沿计数。 校正装置和相关方法形式的装置被配置为至少监视延迟配置输出，用于检测输入间隔的端点与给定时钟信号中所选择的时钟沿的最近出现之间的特定时间关系 这表明增强数据输出中至少存在潜在的错误，并且确定潜在误差是否是后续用于校正增强数据输出的实际误差。
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公开(公告)号：US07633539B2
公开(公告)日：2009-12-15
申请号：US10555890
申请日：2005-06-01
申请人： Yuichiro Yamashita
发明人： Yuichiro Yamashita
IPC分类号： H04N3/14
摘要： In an image pickup device with A/D converters at each column signal line, improvements in the A/D conversion speed and accuracy in image sensors having A/D converters are achieved. In an image pickup device wherein sensing elements are arranged in a matrix and A/D converters are arranged for each column signal line, the A/D converter first retains in its memory unit as an initial value an electric signal corresponding to the signal of the sensing element which is an analog signal, then initiates charge or discharge of the memory unit at a rate corresponding to the size of an input fixed signal, measures the time period from either the charge start time or the discharge start time until the memory unit electric signal becomes equal to the reference signal, and then recognizes the measured time period as a digital value.
摘要翻译： 在具有每列信号线上的A / D转换器的图像拾取装置中，实现了具有A / D转换器的图像传感器的A / D转换速度和精度的改善。 在图像拾取装置中，其中感测元件以矩阵形式布置，并且A / D转换器被布置用于每个列信号线，A / D转换器首先将其存储器单元作为初始值保存，该电信号对应于 感测元件是模拟信号，然后以对应于输入固定信号的大小的速率启动存储器单元的充电或放电，测量从充电开始时间或放电开始时间直到存储单元电 信号变得等于参考信号，然后将测量的时间周期识别为数字值。
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49.发明授权Method for digitizing an analog quantity, digitizing device implementing said method, and electromagnetic radiation detector integrating such a device 有权数字化模拟量的方法，实现所述方法的数字化装置以及集成这种装置的电磁辐射探测器公开(公告)号：US07626529B2
公开(公告)日：2009-12-01
申请号：US11970730
申请日：2008-01-08
申请人： Patrick Robert
发明人： Patrick Robert
IPC分类号： H03M1/12
摘要： A method of digitizing an analog quantity from an electromagnetic radiation detector including a matrix of juxtaposed elementary sensors, including, for each line or column of the matrix, the steps of: integrating the analog quantity using an integrator stage; converting the integrated analog quantity to a first numerical value via a binary counter and a memory element connected to the output of a comparator stage; converting the first numerical value to an analog signal via an analog-to-digital converter; subtracting the analog signal from the analog quantity to be digitized; amplifying the signal resulting from the subtraction with a gain representing the first numerical value; integrating to produce a second numerical value proportional to the analog signal thereby amplified and forming a second binary number representing the least significant bits; and adding said first and second numerical values to form a number representative of the analog quantity to be integrated.
摘要翻译： 一种从包括并置矩阵的基本传感器的电磁辐射检测器数字化模拟量的方法，包括对矩阵的每一行或列进行以下步骤：使用积分器级积分模拟量; 通过二进制计数器和连接到比较器级的输出的存储元件将积分模拟量转换成第一数值; 经由模数转换器将第一数值转换为模拟信号; 从要数字化的模拟量中减去模拟信号; 用代表第一数值的增益放大由减法产生的信号; 积分以产生与模拟信号成比例的第二数值，从而被放大并形成表示最低有效位的第二二进制数; 以及添加所述第一和第二数值以形成表示要被积分的模拟量的数字。
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50.发明授权Analog/digital converter, illuminance sensor, illumination device, and electronic device 有权模拟/数字转换器，照度传感器，照明设备和电子设备公开(公告)号：US07554480B2
公开(公告)日：2009-06-30
申请号：US11775336
申请日：2007-07-10
IPC分类号： H03M1/12
摘要： An analog/digital converter has a charge circuit that has a charge capacitor storing an electric charge commensurate with an input current, and first and second discharge circuits that discharge the electric charge stored in the charge capacitor. While the charge capacitor is charged for a predetermined charge period, every time a predetermined amount of electric charge is stored in the charge capacitor, the electric charge stored there is discharged by the first discharge circuit. After the charge period, the electric charge remaining in the charge capacitor is discharged by the second discharge circuit. Based on the number of discharges performed by the first discharge circuit and the discharge duration of the second discharge circuit, a digital value of the voltage commensurate with the amount of electric charge with which the charge capacitor has been charged is outputted. This offers a wider input dynamic range combined with an enhanced minimum resolution without requiring complicated external control, and in addition allows measurement to be performed in less time.
摘要翻译： 模拟/数字转换器具有充电电路，该充电电路具有存储与输入电流相当的电荷的充电电容器，以及放电存储在充电电容器中的电荷的第一和第二放电电路。 当充电电容器在预定充电期间被充电时，每当在充电电容器中存储预定量的电荷时，存储在其中的电荷被第一放电电路放电。 在充电周期之后，剩余在充电电容器中的电荷被第二放电电路放电。 基于第一放电电路的放电次数和第二放电电路的放电持续时间，输出与充电电容器充电的电荷量相当的电压的数字值。 这提供了更宽的输入动态范围和增强的最小分辨率，而不需要复杂的外部控制，此外允许在更短的时间内执行测量。
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