公开(公告)号：US09210008B2

公开(公告)日：2015-12-08

申请号：US14454420

申请日：2014-08-07

申请人： Texas Instruments Incorporated

发明人： Amit S. Rane

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03 ,  H04L7/00 ,  H04L7/10

CPC分类号： H04L25/03019 ,  H04L7/0087 ,  H04L7/10 ,  H04L25/0286 ,  H04L25/03261 ,  H04L25/03878 ,  H04L25/03885

摘要： A SerDes corn link with a retiming receiver is operable in link training (LT) mode. A SerDes transmitter includes a TX FIR channel driver to transmit TX Data with TX pre-emphasis EQ based on TX FIR coefficients. The retiming receiver includes an RTE (retimer/reclocker) with an RT FIR driver outputting retimed RX Data based on RT FIR coefficients. A link training unit (LTU) adjusts RT FIR coefficients based on a comparison of impulse cursor information for RX Data signals received at the RTE input and re-timed RX Data signals output from the RT FIR, so that the adjusted RT FIR coefficients correspond to the TX FIR coefficients (including reflecting LT changes in TX pre-emphasis EQ). In effect, the LTU performs a linear FIR coefficient translation from the TX FIR to the RT FIR, propagating LT FIR coefficient changes from RTE input to output.

摘要翻译： 具有重定时接收器的SerDes玉米链路可在链路训练（LT）模式中操作。 SerDes发射机包括TX FIR信道驱动器，以基于TX FIR系数的TX预加重EQ发送TX数据。 重定时接收机包括具有RT FIR驱动器的RTE（重新定时器/重新锁定器），其基于RT FIR系数输出重新定时的RX数据。 链路训练单元（LTU）基于在RTE输入端接收到的RX数据信号的脉冲光标信息和从RT FIR输出的重新定时RX数据信号的比较来调整RT FIR系数，使得调整的RT FIR系数对应于 TX FIR系数（包括反映TX预加重EQ中的LT变化）。 实际上，LTU执行从FIR FIR到RT FIR的线性FIR系数转换，将LT FIR系数从RTE输入传播到输出。

公开(公告)号：US09184975B1

公开(公告)日：2015-11-10

申请号：US14548320

申请日：2014-11-20

申请人： The United States of America as represented by the Secretary of the Air Force

发明人： Lihyeh Liou ,  David M. Lin

IPC分类号： H04L27/01 ,  H04L27/38 ,  H04L25/03

CPC分类号： H04L25/03 ,  H04L25/03057 ,  H04L25/03261 ,  H04L25/03343 ,  H04L27/01 ,  H04L27/38 ,  H04L27/3854

摘要： An imbalance compensation system includes a receiver, a first path and a second path electrically coupled to the receiver, and a 90 degree hybrid coupler electrically connected to the second path, wherein the first path is configured to convey an in-phase (I) signal and the second path is configured to convey a quadrature phase (Q) signal. A processor is configured to perform Finite Impulse Response (FIR) filtering upon the I signal and the Q signal, wherein the processor is configured with an inverse matrix of coefficients corresponding to a frequency-dependent phase imbalance and a frequency-dependent amplitude imbalance between the I signal and the Q signal. The processor is configured to perform FIR filtering to attenuate an image signal down to a system noise floor when the processor simultaneously receives signals in a primary Nyquist region and a conjugate Nyquist region.

摘要翻译： 不平衡补偿系统包括接收器，电耦合到接收器的第一路径和第二路径以及电连接到第二路径的90度混合耦合器，其中第一路径被配置为传送同相（I）信号 并且第二路径被配置为传送正交相位（Q）信号。 处理器被配置为对I信号和Q信号执行有限脉冲响应（FIR）滤波，其中处理器配置有与频率相关的相位不平衡和频率相关的幅度不平衡相对应的系数的逆矩阵， I信号和Q信号。 处理器被配置为当处理器在初级奈奎斯特区域和共轭奈奎斯特区域中同时接收信号时，执行FIR滤波以将图像信号衰减到系统本底噪声。

公开(公告)号：US09166615B2

公开(公告)日：2015-10-20

申请号：US14105215

申请日：2013-12-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Martin Kinyua

IPC分类号： H03M1/66 ,  H04L25/03 ,  H03M1/74

CPC分类号： H03M1/661 ,  H03M1/747 ,  H03M3/414 ,  H03M3/50 ,  H03M3/504 ,  H04L25/03261 ,  H04L2025/03363

摘要： A system and method is disclosed for a digital to analog converter which includes an interpolation filter to up-sample a digital signal, a cascaded digital pulse width modulation noise shaper having multiple stages to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to a reconstruction filter which outputs the analog signal. The cascaded noise shaper stages each operate using the same quantization error signal.

摘要翻译： 公开了一种用于数模转换器的系统和方法，该数模转换器包括用于对数字信号进行采样的内插滤波器，具有多级的级联数字脉宽调制噪声整形器，用于抑制由数字脉宽调制引起的带内量化误差， 截断误差，以及耦合到输出模拟信号的重构滤波器的混合有限脉冲响应滤波器/数模转换器。 级联噪声整形器级使用相同的量化误差信号进行操作。

公开(公告)号：US20150155955A1

公开(公告)日：2015-06-04

申请号：US14543856

申请日：2014-11-17

申请人： Realtek Semiconductor Corp.

发明人： Yuan-Shuo Chang ,  Ching-Chia Cheng

IPC分类号： H04B17/00 ,  H04L25/03 ,  H04L27/36

CPC分类号： H04B17/10 ,  H04B17/11 ,  H04B17/14 ,  H04L25/03261 ,  H04L27/366 ,  H04L27/38

摘要： A method for calibrating mismatches of an in-phase signal path and a quadrature signal path of a transmitter, including: additionally configuration at least one mixer calibration coefficient at a transmitting part of the transmitter; obtaining at least one mixer testing signal from the transmitting part via loopback for spectrum analysis to derive at least one mixer spectrum analysis result; adjusting the mixer calibration coefficient of the transmitting part according to the mixer spectrum analysis result; and additionally utilizing an in-phase signal path finite impulse response filter and a quadrature signal path finite impulse response filter to calibrate mismatches between a low pass filter of the in-phase signal path of the transmitting part of the transmitter and a low pass filter of the quadrature signal path of the transmitting part of the transmitter. A similar mismatch calibration operation may be applied to a receiver.

摘要翻译： 一种用于校准发射机的同相信号路径和正交信号路径的不匹配的方法，包括：另外在发射机的发射部分配置至少一个混频器校准系数; 通过环回获得来自发射部分的至少一个混频器测试信号用于频谱分析以得到至少一个混频器频谱分析结果; 根据混频器频谱分析结果调整发射部分的混频器校准系数; 并且另外利用同相信号路径有限脉冲响应滤波器和正交信号路径有限脉冲响应滤波器来校准发射机的发射部分的同相信号路径的低通滤波器与低通滤波器的低通滤波器 发射机发射部分的正交信号路径。 类似的不匹配校准操作可以应用于接收器。

公开(公告)号：US09008161B1

公开(公告)日：2015-04-14

申请号：US14547142

申请日：2014-11-19

申请人： Realtek Semiconductor Corp.

发明人： Yuan-Shuo Chang ,  Ching-Chia Cheng

IPC分类号： H04B1/38 ,  H04L5/16 ,  H04B17/00

CPC分类号： H04B17/10 ,  H04B17/11 ,  H04B17/14 ,  H04L25/03261 ,  H04L27/366 ,  H04L27/38

摘要： A method for calibrating mismatches of an in-phase signal path and a quadrature signal path of a transmitter, including: additionally configuration at least one mixer calibration coefficient at a transmitting part of the transmitter; obtaining at least one mixer testing signal from the transmitting part via loopback for spectrum analysis to derive at least one mixer spectrum analysis result; adjusting the mixer calibration coefficient of the transmitting part according to the mixer spectrum analysis result; and additionally utilizing an in-phase signal path finite impulse response filter and a quadrature signal path finite impulse response filter to calibrate mismatches between a low pass filter of the in-phase signal path of the transmitting part of the transmitter and a low pass filter of the quadrature signal path of the transmitting part of the transmitter. A similar mismatch calibration operation may be applied to a receiver.

公开(公告)号：US07551701B1

公开(公告)日：2009-06-23

申请号：US10816781

申请日：2004-04-02

申请人： Sirikiat L. Ariyavisitakul ,  Manoneet Singh

发明人： Sirikiat L. Ariyavisitakul ,  Manoneet Singh

IPC分类号： H04B1/10

CPC分类号： H04L25/022 ,  H04L25/03261 ,  H04L25/03292 ,  H04L2025/03426

摘要： Prefilters for a receiver with multiple input branches are trained in the frequency domain. The frequency response B of a conditioned channel is determined without reference to the prefilters, and the frequency response W of the prefilters is computed from the frequency response B of the conditioned channel. The prefilters suppress interference.

摘要翻译： 具有多个输入分支的接收机的预滤波器在频域中被训练。 在不参考前置滤波器的情况下确定经调理的信道的频率响应B，并且根据调理信道的频率响应B来计算预滤波器的频率响应W. 前置滤波器抑制干扰。

公开(公告)号：US20080159377A1

公开(公告)日：2008-07-03

申请号：US12043517

申请日：2008-03-06

申请人： Steve A. Allpress ,  Quinn Li

发明人： Steve A. Allpress ,  Quinn Li

IPC分类号： G06F17/10 ,  H03H7/30

CPC分类号： H04L25/03261 ,  H04L25/03057 ,  H04L25/03076 ,  H04L25/03146 ,  H04L25/03171 ,  H04L2025/03401 ,  H04L2025/0349 ,  H04L2025/0356 ,  H04L2025/03796

摘要： An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1

摘要翻译： （1）将判决反馈均衡器（DFE）与最大后缀（MAP）均衡器（或最大似然序列估计器，MLSE）（2）的优点相结合的均衡器的装置和方法（2）执行均衡 基于信道是最小相位或最大相位的时间前向或时间反转方式来提供具有比全状态MAP设备显着更低的复杂度的均衡设备，但仍然提供比常规DFE更好的性能。 均衡器架构包括两个类似DFE的结构，其次是MAP均衡器。 第一个DFE形成暂定的符号决定。 此后使用第二DFE来截断对于L1 L1符号的期望存储器的信道响应，其小于信道的L个符号的总延迟扩展。 MAP均衡器在具有L 1 1符号（其中L 1> L =）的存储器的信道上操作，因此均衡器的总体复杂度显着降低。

公开(公告)号：US07151796B2

公开(公告)日：2006-12-19

申请号：US09946648

申请日：2001-09-04

申请人： Steve A. Allpress ,  Quinn Li

发明人： Steve A. Allpress ,  Quinn Li

IPC分类号： G06F17/10 ,  H03H7/30

CPC分类号： H04L25/03261 ,  H04L25/03057 ,  H04L25/03076 ,  H04L25/03146 ,  H04L25/03171 ,  H04L2025/03401 ,  H04L2025/0349 ,  H04L2025/0356 ,  H04L2025/03796

摘要： An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1

摘要翻译： （1）将判决反馈均衡器（DFE）与最大后缀（MAP）均衡器（或最大似然序列估计器，MLSE）（2）的优点相结合的均衡器的装置和方法（2）执行均衡 基于信道是最小相位或最大相位的时间前向或时间反转方式来提供具有比全状态MAP设备显着更低的复杂度的均衡设备，但仍然提供比常规DFE更好的性能。 均衡器架构包括两个类似DFE的结构，其次是MAP均衡器。 第一个DFE形成暂定的符号决定。 此后使用第二DFE来截断对于L1 L1符号的期望存储器的信道响应，其小于信道的L个符号的总延迟扩展。 MAP均衡器在具有L 1 1符号（其中L 1> L =）的存储器的信道上操作，因此均衡器的总体复杂度显着降低。

公开(公告)号：US20060120446A1

公开(公告)日：2006-06-08

申请号：US11344406

申请日：2006-01-31

申请人： Steve Allpress ,  Quinn Li

发明人： Steve Allpress ,  Quinn Li

IPC分类号： H03H7/30 ,  H04B1/10

CPC分类号： H04L25/03261 ,  H04L25/03057 ,  H04L25/03076 ,  H04L2025/03401 ,  H04L2025/0356 ,  H04L2025/03796

摘要： This invention describes an apparatus and method to improve the performance of a decision feedback equalizer (DFE) for time-varying multi-path channels. For minimum-phase channels, the equalization is performed in a time-forward manner. For maximum-phase channels, the equalization is performed in a time-reversed manner. More specifically, for maximum-phase channels, the filter coefficients are computed based on the channel estimates reversed in time, and the filtering and equalization operations are performed with the received block of symbols in a time-reversed order. In the context of this invention, the term “minimum-phase channel” implies that the energy of the leading part of the channel profile is greater than the energy of the trailing part. The term “maximum-phase channel” implies that the energy of the leading part of the channel profile is less than the energy of the trailing part.

公开(公告)号：US07012957B2

公开(公告)日：2006-03-14

申请号：US09941300

申请日：2001-08-27

申请人： Stephen Allpress ,  Quinn Li

发明人： Stephen Allpress ,  Quinn Li

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L25/03171 ,  H04L25/03057 ,  H04L25/03076 ,  H04L25/03146 ,  H04L25/03261 ,  H04L2025/03401 ,  H04L2025/0349 ,  H04L2025/0356 ,  H04L2025/03796

摘要： An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1

摘要翻译： 一种用于实现均衡器的装置和方法，其将判决反馈均衡器（DFE）与最大似然序列估计器（MLSE）的最大似然序列估计器（MLSE）的优点相结合，以提供具有显着更低复杂度的均衡器件 而不是全状态MAP设备，但仍然提供比传统DFE更好的性能。 均衡器架构包括两个类似DFE的结构，其次是MAP均衡器。 第一个DFE形成暂定的符号决定。 此后使用第二DFE来截断对于L1 L1符号的期望存储器的信道响应，其小于信道的L个符号的总延迟扩展。 MAP均衡器在具有L 1 1符号（其中L 1> L =）的存储器的信道上操作，因此均衡器的总体复杂度显着降低。