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公开(公告)号：US09468092B2
公开(公告)日：2016-10-11
申请号：US14405572
申请日：2014-10-08
Inventor： Tomoaki Sawada , Shingo Yoshioka , Takatoshi Abe
IPC: B32B3/12 , B32B3/24 , B32B15/08 , B32B15/092 , G06F3/041 , H01B1/02 , H01L31/0224 , H05K1/03 , H05K1/02 , C08J5/18 , C08K7/02 , C08L101/00 , C08J7/04 , C09D105/16 , B32B3/26
CPC classification number: H05K1/0271 , B32B3/12 , B32B3/266 , B32B5/02 , B32B15/08 , B32B15/092 , B32B2260/021 , B32B2260/046 , B32B2262/103 , B32B2262/106 , B32B2262/14 , B32B2307/202 , B32B2307/412 , B32B2307/50 , B32B2363/00 , C08J5/18 , C08J7/047 , C08J2300/21 , C08J2367/02 , C08J2400/21 , C08J2463/00 , C08K7/02 , C08L101/00 , C09D105/16 , C09D163/00 , G06F3/041 , H01B1/02 , H01B1/24 , H01L31/022466 , H01L31/022491 , H05K1/0213 , H05K1/0274 , H05K1/028 , H05K1/0296 , H05K1/0326 , H05K1/0333 , H05K1/0366 , H05K2201/0108 , H05K2201/012 , H05K2201/0323 , H05K2201/0326 , Y10T428/24331 , Y10T428/24917 , C08L63/00
Abstract: The present invention relates to an electrically conductive film characterized by being able to undergo elastic deformation, having little residual strain rate and exhibiting stress relaxation properties. More specifically, the present invention relates to an electrically conductive film wherein the stress relaxation rate (R) and the residual strain rate α, as measured in a prescribed extension-restoration test, are as follows: 20%≦R≦95% and 0%≦α≦3%.
Abstract translation: 本发明涉及一种导电膜，其特征在于能够进行弹性变形，几乎没有残余应变率和显示应力松弛性能。 更具体地说，本发明涉及一种导电膜，其中在规定的延伸恢复试验中测量的应力松弛率（R）和残余应变速率α如下：20％≤R≤95％和0 ％≤α≤3％。
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公开(公告)号：US20160150652A1
公开(公告)日：2016-05-26
申请号：US14905241
申请日：2014-07-15
Applicant: NOVALIA LTD
Inventor： Kate Stone
CPC classification number: H05K1/189 , H01L23/13 , H01L23/49811 , H01L23/49838 , H01L23/49855 , H01L23/5386 , H01L23/5387 , H01L23/5388 , H01L2924/0002 , H05K1/0213 , H05K2201/09218 , H01L2924/00
Abstract: An article comprises an electronic component, such as an integrated circuit or packaged integrated circuit, and a circuit sheet arrangement. The circuit sheet arrangement may comprise a flexible planar substrate and conductive tracks formed on a face of the substrate. The substrate is configured to have an aperture enclosed by surrounding portion of the substrate and to have at least two arms supporting respective conductive tracks which extend into the aperture from the surrounding portions. The electronic component is disposed over the aperture and is attached to conductive tracks on the arms, for example, using conductive glue or ink.
Abstract translation: 一种物品包括诸如集成电路或封装集成电路的电子部件和电路板布置。 电路板布置可以包括柔性平面基板和形成在基板的表面上的导电轨道。 衬底被配置为具有由衬底的周围部分包围的孔，并且具有支撑从周围部分延伸到孔中的相应导电轨道的至少两个臂。 电子部件设置在孔的上方，并且例如使用导电胶或油墨附接到臂上的导电轨道上。
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公开(公告)号：US20160150637A1
公开(公告)日：2016-05-26
申请号：US14442470
申请日：2013-11-13
Applicant: Amichai ZIV
Inventor： Amichai ZIV
CPC classification number: H05K1/0213 , B05C17/005 , B25H7/04 , B43K8/02 , B43K19/00 , G01R31/025 , H01C7/00 , H05K3/28
Abstract: The present invention relates to a kit devise, and method for absorbing leakage current in an electronic circuit including at least one switch and at least one load by using an absorbing device, an absorbing material or an absorbent marking device, wherein the absorbent marking device is configured to mark or attach an absorbing material on the circuit or on the load.
Abstract translation: 本发明涉及一种用于通过使用吸收装置，吸收材料或吸收性标记装置吸收包括至少一个开关和至少一个负载的电子电路中的漏电流的方法，其中吸收标记装置是 被配置为在电路或负载上标记或附着吸收材料。
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公开(公告)号：US20160120024A1
公开(公告)日：2016-04-28
申请号：US14881567
申请日：2015-10-13
Applicant: IRISO ELECTRONICS CO., LTD.
Inventor： Jun Oguro
CPC classification number: H05K1/0213 , H01R4/48 , H01R4/4818 , H01R12/515 , H01R12/55 , H01R12/57 , H01R13/111 , H05K1/184 , H05K2201/10189 , H05K2201/10265 , H05K2201/10287 , H05K2201/10295
Abstract: A linear conductor connection terminal that is fixed to a substrate and that comes in contact in a conductive manner with a linear conductor that is inserted in a hole portion provided in the substrate. The linear conductor connection terminal includes a contact portion that is positioned inside the hole portion and that comes in contact in the hole portion with the linear conductor in a conductive manner; an elastic piece that elastically supports the contact portion; a top surface portion provided so as to be spaced apart from the contact portion in an insertion direction of the linear conductor, the top surface portion including an insertion hole to introduce the linear conductor to the contact portion; and a first leg portion and a second leg portion that support the top surface portion that is spaced apart from the contact portion.
Abstract translation: 一种线性导体连接端子，其固定到基板并且以导电方式与插入设置在基板中的孔部分中的线性导体接触。 线状导体连接端子包括位于孔部内部并以导电方式与线状导体接触的接触部， 弹性片，其弹性地支撑所述接触部; 所述顶表面部分设置成在所述线状导体的插入方向上与所述接触部分间隔开，所述顶表面部分包括用于将所述线性导体引入所述接触部分的插入孔; 以及第一腿部和第二腿部，其支撑与接触部分间隔开的顶表面部分。
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公开(公告)号：US09326369B2
公开(公告)日：2016-04-26
申请号：US13921550
申请日：2013-06-19
Applicant: Keithley Instruments, Inc.
Inventor： James A. Niemann , Gregory Sobolewski , Martin J. Rice , Wayne Goeke
CPC classification number: H05K1/0213 , H05K1/0225 , H05K1/0256 , H05K1/142 , H05K1/145 , H05K3/306 , H05K3/4038 , H05K3/4697 , H05K2201/0792 , H05K2201/09063 , H05K2201/093 , H05K2201/09618 , H05K2201/0969 , H05K2201/09981 , Y10T29/49139
Abstract: A device with low dielectric absorption includes a printed circuit board (PCB), a component connection area including a first conductor layered on a top surface of the component connection area and a second conductor layered on a bottom surface of the component connection area, an aperture surrounding the component connection area, a low-leakage component connecting the component connection area to the PCB across the aperture, and a guard composed of a third conductor at least substantially surrounding the aperture on a top surface of the PCB and a fourth conductor at least substantially surrounding the aperture on a bottom surface of the PCB.
Abstract translation: 具有低介电吸收率的器件包括印刷电路板（PCB），包括层叠在部件连接区域的顶表面上的第一导体的部件连接区域和层叠在部件连接区域的底表面上的第二导体， 围绕部件连接区域，将部件连接区域连接到穿过孔的PCB的低泄漏部件以及由至少基本上围绕PCB顶表面上的孔的第三导体组成的防护件和至少 基本上围绕PCB的底表面上的孔。
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46.发明申请ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND FLAT PANEL DISPLAY DEVICE 审中-公开阵列基板，其制造方法和平板显示装置
公开(公告)号：US20160057871A1
公开(公告)日：2016-02-25
申请号：US14918623
申请日：2015-10-21
Inventor： Li CHAI
CPC classification number: H05K3/4644 , G02F1/1345 , G02F2001/13629 , H01L27/124 , H05K1/0213 , H05K3/06 , H05K3/22 , H05K3/4038 , H05K2201/0338 , H05K2201/0784
Abstract: A method for manufacturing an array substrate includes a step of forming a first metal layer on a glass substrate such that the first metal layer includes multiple first metal lines distributed as a fan shape, each of the first metal lines including a predetermined number of first metal strip portions that are spaced from each other and have an equal length; forming an insulation layer on the multiple first metal lines in such a way that portions of the insulation layer respectively covering the first metal strip portions are each provided with a first through hole and a second through hole formed therein; and forming a second metal layer on the insulation layer such that the second metal layer includes multiple second metal strip portions respectively in contact with the first metal strip portions of the first metal lines via the first through holes and the second through holes.
Abstract translation: 一种阵列基板的制造方法，其特征在于，在玻璃基板上形成第一金属层，使得所述第一金属层包含分散为扇形的多个第一金属线，所述第一金属线包含规定数量的第一金属 带状部分彼此间隔开并具有相等的长度; 在所述多个第一金属线上形成绝缘层，使得分别覆盖所述第一金属带部的所述绝缘层的各部分分别设置有形成在其中的第一通孔和第二通孔; 以及在所述绝缘层上形成第二金属层，使得所述第二金属层包括分别经由所述第一通孔和所述第二通孔与所述第一金属线的所述第一金属带部分接触的多个第二金属带部分。
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公开(公告)号：US20150318596A1
公开(公告)日：2015-11-05
申请号：US14702194
申请日：2015-05-01
Applicant: IBIDEN CO., LTD.
Inventor： Yasushi INAGAKI , Yasuhiro TAKAHASHI , Satoshi KUROKAWA
CPC classification number: H01P3/081 , H05K1/0213 , H05K1/0228 , H05K1/0243 , H05K1/0251 , H05K1/111 , H05K1/181 , H05K3/3436 , H05K3/429 , H05K2201/10159
Abstract: A package substrate includes a core substrate, a first buildup layer and a second buildup layer. The first buildup layer includes an uppermost interlayer, an upper inner interlayer, an uppermost conductive layer including first pads and second pads, an upper first conductive layer, an upper second conductive layer, vias formed through the uppermost interlayer and connecting the upper first conductive layer and the second pads, and skip vias formed through the uppermost and upper inner interlayers and connecting the uppermost and upper second conductive layers. The second buildup layer includes a lowermost interlayer, a lower inner interlayer, a lowermost conductive layer including third pads, a lower first conductive layer, a lower second conductive layer, vias formed through the lowermost interlayer and connecting the lower first conductive layer and third pads, and skip vias formed through the lowermost and lower inner interlayers and connecting the lowermost and lower second conductive layers.
Abstract translation: 封装基板包括芯基板，第一堆积层和第二堆积层。 第一累积层包括最上层中间层，上内层中间层，包括第一焊盘和第二焊盘的最上层导电层，上第一导电层，上第二导电层，通过最上层中间层形成的通孔，并将上第一导电层 和第二焊盘，并且跳过通过最上层和上部内中间层形成的通孔，并连接最上面和上部第二导电层。 第二堆积层包括最下层的中间层，下层的内层，包含第三层的最下层的导电层，下部的第一导电层，下部的第二导电层，通过最下层的中间层形成的通孔，并连接下部第一导电层和第三层 并且跳过通过最下部和下部内部中间层形成的通孔并连接最下部和下部第二导电层。
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公开(公告)号：US20150313005A1
公开(公告)日：2015-10-29
申请号：US14406913
申请日：2012-06-15
Applicant: Masashi TAKABATAKE , Kenji KASHIWAGI
Inventor： Masashi TAKABATAKE , Kenji KASHIWAGI
CPC classification number: H05K1/0213 , H05K1/025 , H05K1/0253 , H05K1/111 , H05K3/3421 , H05K2201/0776 , H05K2201/09372 , H05K2201/0969 , H05K2201/10189 , Y02P70/611
Abstract: [Object] There is suggested a printed circuit board capable of realizing impedance matching by securing joint reliability between signal pins of a surface mount connector and signal pin pads and preventing the reduction of impedance of signal pin pads while minimizing the reduction of a wirable area.[Solution] A printed circuit board equipped with a signal pin pad, which is soldered to a signal pin from a surface mount connector, and a ground layer located as a lower layer below the signal pin pad; wherein a fillet is formed around a joint area between the signal pin and the signal pin pad after soldering; wherein a cut-out portion is provided in the signal pin pad within a joint area with the signal pin; and wherein the size of the cut-out portion is set within the range of being completely covered within the joint area with the signal pin based on size tolerance of the signal pin, fabrication tolerance of the printed circuit board, and mount position tolerance of the surface mount connector.
Abstract translation: 提出了一种印刷电路板，其能够通过确保表面安装连接器的信号引脚和信号引脚焊盘之间的连接可靠性来实现阻抗匹配，并且防止信号引脚焊盘的阻抗减小，同时最小化可吸收区域的减少。 [解决方案]配备有从表面安装连接器焊接到信号引脚的信号引脚焊盘的印刷电路板和位于信号引脚焊盘下方的下层的接地层; 其中在焊接之后，在信号引脚和信号引脚焊盘之间的接合区域周围形成圆角; 其中在与所述信号引脚的接合区域内的所述信号引脚焊盘中设置切口部分; 并且其中，根据信号引脚的尺寸公差，印刷电路板的制造公差以及印刷电路板的安装位置公差，将切除部分的尺寸设定在与信号销的接合区域内完全覆盖的范围内 表面贴装连接器。
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公开(公告)号：US20150282313A1
公开(公告)日：2015-10-01
申请号：US14428526
申请日：2013-09-17
Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
Inventor： Kiminori Ozaki , Yasuhiro Koike , Hiroaki Asano , Hitoshi Shimazu , Tomoaki Asai
CPC classification number: H05K1/11 , H01L2924/19105 , H01L2924/19107 , H05K1/0213 , H05K1/142 , H05K1/181 , H05K3/0073 , H05K3/36 , H05K3/368 , H05K3/4069 , H05K2201/0305 , H05K2201/09145 , H05K2201/10287 , H05K2201/2072 , H05K2203/043 , Y10T29/49126
Abstract: A wiring board includes a first substrate including a first surface and a second substrate including a first surface. A solder hole is arranged at least in the first surface of the first substrate. A solder hole is arranged at least in the first surface of the second substrate. The second substrate is coupled to the first substrate. The first substrate and the second substrate are electrically connected with each other. The first surface of the first substrate and the first surface of the second substrate are flush with each other and configured such that a part of one surface of a mask is placed on the first surface of the first substrate and another part of the surface of the mask is placed on the first surface of the second substrate.
Abstract translation: 布线基板包括包括第一表面的第一基板和包括第一表面的第二基板。 至少在第一基板的第一表面中布置有焊料孔。 至少在第二基板的第一表面中布置有焊料孔。 第二衬底耦合到第一衬底。 第一基板和第二基板彼此电连接。 第一基板的第一表面和第二基板的第一表面彼此齐平并且被配置为使得掩模的一个表面的一部分被放置在第一基板的第一表面上，另一部分表面的 掩模放置在第二基板的第一表面上。
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50.发明授权
公开(公告)号：US09145618B2
公开(公告)日：2015-09-29
申请号：US13990388
申请日：2011-11-29
Applicant: Asli Sirman , Ahmed Busnaina , Cihan Yilmaz , Jun Huang , Sivasubramanian Somu
Inventor： Asli Sirman , Ahmed Busnaina , Cihan Yilmaz , Jun Huang , Sivasubramanian Somu
CPC classification number: C25D13/22 , B82Y30/00 , B82Y40/00 , C09D5/4407 , C09D5/4488 , C09D125/06 , C25D13/04 , C25D13/12 , C25D13/20 , H01L21/0243 , H01L21/0259 , H01L21/02628 , H01L29/0665 , H05K1/0213 , H05K1/0306 , H05K1/092 , H05K3/1258 , Y10S977/882 , Y10S977/892
Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.
Abstract translation: 将纳米元件高速组装成非导电基底表面上的二维空穴图案的方法利用施加的电场来抵抗通过纳米元素悬浮液的表面拉动基底所产生的力。 由绝缘层覆盖的衬底中的导电层发出的电场轮廓由图案化的光致抗蚀剂层改变，导致纳米元件从液体悬浮液迁移到具有非绝缘层的图案化衬底上的空隙的驱动力增加， 导电表面。 该方法可用于生产微尺度和纳米级电路，传感器和其他电子设备。
