公开(公告)号：US07549678B2

公开(公告)日：2009-06-23

申请号：US11247339

申请日：2005-10-11

申请人： Erik M. Howard ,  Charles Armbrust

发明人： Erik M. Howard ,  Charles Armbrust

IPC分类号： F16L17/00

CPC分类号： F16L37/62 ,  Y10S285/92

摘要： Systems for actuating a pair of pipe flanges to cause the flanges to be sealingly engaged. In one embodiment, a connection includes a first flange, a second flange and a coupling. The first and second flanges have complementary mating surfaces. The coupling engages both the first and second flanges, with the flanges oriented so that their mating surfaces face each other. The coupling movably engages the first flange to form a cavity between the coupling and the flange. When fluid is forced into the cavity, expansion of the cavity moves the first mating surface toward the second mating surface. This is continued until the mating surfaces make contact and a desired amount of pressure is applied between them to create a seal. The pressure of the fluid is distributed evenly through the cavity, so the contact pressure between the mating surfaces of the flanges is also evenly distributed.

摘要翻译： 用于致动一对管道凸缘以使凸缘密封接合的系统。 在一个实施例中，连接包括第一凸缘，第二凸缘和联接件。 第一和第二凸缘具有互补的配合表面。 联接器接合第一和第二凸缘，其中凸缘定向成使得它们的配合表面彼此面对。 联接器可移动地接合第一凸缘以在联接器和凸缘之间形成空腔。 当流体被迫进入空腔时，腔的膨胀将第一配合表面朝向第二配合表面移动。 这直到配合表面接触并且在它们之间施加期望的压力以产生密封。 流体的压力均匀地分布在空腔中，因此凸缘的配合表面之间的接触压力也均匀分布。

公开(公告)号：US07536535B2

公开(公告)日：2009-05-19

申请号：US11379681

申请日：2006-04-21

申请人： Paul B. Wood

发明人： Paul B. Wood

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30145 ,  G06F9/30181 ,  G06F9/3869 ,  G06F9/3871

摘要： Systems and methods for executing program instructions in a data processor at a variable rate. In one embodiment, a processor is configured to examine received instructions, identify an execution time associated with each instruction, and generate clock pulses at necessary intervals to obtain the appropriate execution time for each instruction. Instructions may be associated with types or “bins” that are in turn associated with corresponding execution times. The clock pulses may be generated by routing successive pulses through circuits that delay the pulses by desired amounts of time. The processor may also be configured to identify instructions which are input/output (I/O) instructions and are initiated or terminated by completion of handshake procedures and therefore have execution times that vary from one instance to the next.

摘要翻译： 用于以可变速率执行数据处理器中的程序指令的系统和方法。 在一个实施例中，处理器被配置为检查接收到的指令，识别与每个指令相关联的执行时间，并且以必要的间隔生成时钟脉冲以获得每个指令的适当执行时间。 指令可能与相应的执行时间相关联的类型或“仓”相关联。 时钟脉冲可以通过将连续的脉冲路由到将脉冲延迟期望的时间量的电路来产生。 处理器还可以被配置为识别作为输入/输出（I / O）指令的指令，并且通过完成握手过程来启动或终止指令，因此具有从一个实例到下一个实例的执行时间。

公开(公告)号：US07492570B2

公开(公告)日：2009-02-17

申请号：US11105113

申请日：2005-04-13

申请人： Eiichi Hosomi ,  Paul M. Harvey

发明人： Eiichi Hosomi ,  Paul M. Harvey

IPC分类号： H01G4/228

CPC分类号： H01L23/50 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/19106 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/182 ,  H05K2201/09072 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00

摘要： Systems and methods for reducing switching noise in an integrated circuit. In one embodiment, decoupling capacitors are connected to the integrated circuit from the underside of the substrate on which the integrated circuit die is manufactured. The decoupling capacitors are positioned with a higher concentration in the “hot spot” areas of the integrated circuit instead of being evenly distributed. In one embodiment, the decoupling capacitors and the corresponding hole(s) in a circuit board on which the integrated circuit is mounted are positioned so that the circuit board provides support for the central portion of the integrated circuit and thereby prevents the integrated circuit from flexing away from the heat sink/spreader. In one embodiment, the concentration of vias connecting the different ground planes and/or power planes within the integrated circuit is higher in hot spots than in other areas.

摘要翻译： 用于降低集成电路中的开关噪声的系统和方法。 在一个实施例中，去耦电容器从其上制造集成电路芯片的基板的下侧连接到集成电路。 去耦电容器在集成电路的“热点”区域中以更高的浓度定位，而不是均匀分布。 在一个实施例中，在其上安装集成电路的电路板中的去耦电容器和相应的孔定位成使得电路板为集成电路的中心部分提供支撑，从而防止集成电路弯曲 远离散热器/吊具。 在一个实施例中，连接集成电路内的不同接地层和/或电源层的通孔的浓度在热点中高于其它区域。

公开(公告)号：US07482865B2

公开(公告)日：2009-01-27

申请号：US11672331

申请日：2007-02-07

申请人： Michael A. Kost ,  Jack B. Andersen ,  Daniel L. W. Chieng

发明人： Michael A. Kost ,  Jack B. Andersen ,  Daniel L. W. Chieng

IPC分类号： H03F3/38

CPC分类号： H03F3/2173 ,  H03F1/30 ,  H03F1/34 ,  H03F2200/03 ,  H03F2200/351

摘要： Systems and methods for minimizing performance degradation due to component mismatch in the feedback path of a digital PWM amplifier feedback loop. One embodiment comprises a digital pulse width modulated (PWM) amplifier with feedback. The amplification subsystem receives a digital audio signal and produces an analog output signal. The feedback loop produces a feedback signal based on the filtered analog output signal and modifies the digital audio signal based on the feedback signal. The feedback loop includes a filter configured to filter the analog output signal and correction circuitry configured to correct component mismatch errors introduced by the filter. In one embodiment, the correction circuitry receives a measurement of a power supply voltage, multiplies the measured voltage by a gain and adds the scaled measurement to the feedback signal to correct for the component mismatch errors.

摘要翻译： 用于使数字PWM放大器反馈回路的反馈路径中的组件不匹配导致性能下降最小化的系统和方法。 一个实施例包括具有反馈的数字脉宽调制（PWM）放大器。 放大子系统接收数字音频信号并产生模拟输出信号。 反馈回路基于滤波的模拟输出信号产生反馈信号，并且基于反馈信号修改数字音频信号。 反馈回路包括被配置为过滤模拟输出信号的滤波器和被配置为校正由滤波器引入的元件失配误差的校正电路。 在一个实施例中，校正电路接收电源电压的测量，将测量的电压乘以增益，并将缩放的测量值加到反馈信号上，以校正组件失配误差。

公开(公告)号：US07362254B2

公开(公告)日：2008-04-22

申请号：US11669305

申请日：2007-01-31

申请人： Michael A. Kost

发明人： Michael A. Kost

IPC分类号： H03M1/12

CPC分类号： H03F3/217 ,  H03F2200/03 ,  H03F2200/351 ,  H03M3/37 ,  H03M3/506

摘要： Systems and methods for minimizing delay in a feedback path. In one embodiment, an analog-to-digital feedback path includes an analog-to-digital converter (ADC) configured to receive and digitize an analog signal such as an amplifier output to produce a serial digital output. A serial interface receives and parallelizes the serial digital output to produce a parallel data words that are provided to a processing unit such as a decimator. The processing unit processes the data words to produce a digital feedback signal which can then be used to modify an input signal, such as a digital audio input to the amplifier. A delay minimization subsystem is implemented in the feedback path to monitor a delay between generation of parallel data words by the serial interface and consumption of the parallel data words by the first processing unit. The delay minimization mechanism may be implemented in multiple channels of the feedback path.

摘要翻译： 用于最小化反馈路径延迟的系统和方法。 在一个实施例中，模数 - 数字反馈路径包括被配置为接收和数字化模拟信号（例如放大器输出）以产生串行数字输出的模拟 - 数字转换器（ADC）。 串行接口接收和并行串行数字输出，以产生提供给诸如抽取器之类的处理单元的并行数据字。 处理单元处理数据字以产生数字反馈信号，该数字反馈信号然后可用于修改输入信号，例如输入到放大器的数字音频。 在反馈路径中实现延迟最小化子系统，以监视由串行接口产生并行数据字之间的延迟和第一处理单元对并行数据字的消耗。 延迟最小化机制可以在反馈路径的多个通道中实现。

公开(公告)号：US07259618B2

公开(公告)日：2007-08-21

申请号：US11211765

申请日：2005-08-25

申请人： Larry E. Hand ,  Wilson E. Taylor

发明人： Larry E. Hand ,  Wilson E. Taylor

IPC分类号： H03F3/38 ,  H03F1/52 ,  G01R19/00

CPC分类号： H03F3/2173 ,  H03F1/523 ,  H03F3/2175 ,  H03F2200/331 ,  H03F2200/426

摘要： Systems and methods for detecting the impedance of an output load coupled to a digital amplifier and compensating for changes in the response of the amplifier. One embodiment of the invention is implemented in a Class D pulse width modulated (PWM) amplifier. In this embodiment, a digital PCM test signal is generated. This test signal is processed by the amplifier to produce a corresponding analog audio output signal that is used to drive a speaker. A sense resistor placed in series with the speaker is used to generate a test voltage that is compared to a reference voltage. When the test voltage reaches the reference voltage, the current through the sense resistor (hence the speaker) is at a known level, so the value of the digital test signal is noted. The impedance of the speaker is then determined from the test signal value and the speaker current.

摘要翻译： 用于检测耦合到数字放大器的输出负载的阻抗并补偿放大器的响应的变化的系统和方法。 本发明的一个实施例在D类脉宽调制（PWM）放大器中实现。 在本实施例中，产生数字PCM测试信号。 该测试信号由放大器处理以产生用于驱动扬声器的对应的模拟音频输出信号。 使用与扬声器串联放置的检测电阻器来产生与参考电压相比较的测试电压。 当测试电压达到参考电压时，通过检测电阻器（因此扬声器）的电流处于已知电平，因此记录数字测试信号的值。 然后从测试信号值和扬声器电流确定扬声器的阻抗。

公开(公告)号：US07218152B2

公开(公告)日：2007-05-15

申请号：US11033612

申请日：2005-01-12

申请人： Hiroaki Murakami ,  Osamu Takahashi ,  Shoji Onishi

发明人： Hiroaki Murakami ,  Osamu Takahashi ,  Shoji Onishi

IPC分类号： H03K19/20

CPC分类号： H03K19/1737

摘要： Systems and methods for reducing the power consumption associated with the capacitance of sections of a multiplexer are disclosed. At each cycle, a timing signal is selectively sent only to sections of the multiplexer that include active logic. A plurality of control signals is received for processing by a corresponding plurality of input selection circuits. A plurality of additional inputs corresponding to the plurality of input selection circuits may also be received. In one embodiment, each input selection circuit is configured to output a corresponding input signal if a corresponding control signal is asserted and a timing signal is made available to the input selection circuit. To avoid unnecessary power consumption associated with the capacitance of various portions of the multiplexer, the timing signal is only asserted to a portion of the multiplexer at any given clock cycle according to the values of the control signals.

摘要翻译： 公开了用于降低与多路复用器的部分的电容相关联的功耗的系统和方法。 在每个周期，定时信号仅选择性地仅发送到包括有效逻辑的多路复用器的部分。 多个控制信号被接收用于由相应的多个输入选择电路进行处理。 还可以接收对应于多个输入选择电路的多个附加输入。 在一个实施例中，每个输入选择电路被配置为如果相应的控制信号被断言并且使定时信号对输入选择电路可用，则输出相应的输入信号。 为了避免与多路复用器的各个部分的电容相关联的不必要的功率消耗，定时信号仅根据控制信号的值以任何给定的时钟周期被认定到多路复用器的一部分。

公开(公告)号：US07203780B2

公开(公告)日：2007-04-10

申请号：US11063174

申请日：2005-02-22

申请人： Shigehiro Asano ,  Tsutomu Ishii

发明人： Shigehiro Asano ,  Tsutomu Ishii

IPC分类号： G00F13/00

CPC分类号： G06F13/4221

摘要： Systems and methods for enabling a slave device to generate a tag that is an index into a buffer where the slave device stores information related to an active transaction such as a write command received by a master device. The tag is sent to the master device with a reply (such as a response to a write command received from the master device), the master device returns the tag with the data to be written to the slave device. The slave device can efficiently associate the received data with the previously sent write command by retrieving the command from the buffer using the tag as an index into the buffer. Additional hardware such as a content-addressable memory unit is not required to make the association.

摘要翻译： 用于使从设备能够生成作为缓存器的索引的标签的系统和方法，其中从设备存储与主设备接收的诸如写命令之类的活动事务相关的信息。 标签通过回复（例如对从主设备接收到的写命令的响应）发送到主设备，主设备将具有要写入从设备的数据的标签返回。 从设备可以通过使用标签作为缓冲器的索引从缓冲器中检索命令来有效地将接收到的数据与先前发送的写入命令相关联。 不需要诸如内容寻址存储器单元的附加硬件来进行关联。

公开(公告)号：US07170312B2

公开(公告)日：2007-01-30

申请号：US11017265

申请日：2004-12-20

申请人： Atsushi Kawasumi

发明人： Atsushi Kawasumi

IPC分类号： H03K17/16

CPC分类号： H03K19/0963

摘要： Systems and methods for reducing variations in the timing of signal transitions which may result from interference with neighboring signal lines by adjusting the drivability of in-line buffers based upon the hostile/friendly condition of the neighboring lines. In one embodiment, a first inverter includes selectable current paths between the buffer output and Vdd/ground. A higher current is selected for one path and a lower current is selected for the other path so that the buffer output will be pulled more strongly in the direction (Vdd/ground) to which the neighboring signals may be hostile. In one embodiment, each selectable current path includes a plurality of parallel transistors, one of which is always switched on and the others of which are switched on or off according to the friendly/hostile states of the neighboring signals.

摘要翻译： 基于相邻线路的敌对/友好状况调整直线缓冲器的驾驶性能，减少信号转换时序变化的系统和方法。 在一个实施例中，第一反相器包括在缓冲器输出和Vdd /地之间的可选择的电流路径。 对于一个路径选择较高的电流，并且为另一个路径选择较低的电流，使得缓冲器输出将在相邻信号可能是敌对的方向（Vdd /地）上被更强地拉出。 在一个实施例中，每个可选择的电流路径包括多个并联晶体管，其中一个平行晶体管总是被接通，其它的并联晶体根据相邻信号的友好/敌对状态而被接通或断开。

公开(公告)号：US09893578B2

公开(公告)日：2018-02-13

申请号：US14693249

申请日：2015-04-22

申请人： Baker Hughes Incorporated

发明人： James C. Clingman ,  Chad A. Craig

IPC分类号： H02K1/27 ,  H02K1/28 ,  H02K5/132

CPC分类号： H02K1/276 ,  H02K5/132 ,  H02K2201/06

摘要： Systems and methods for constructing electric motors in which rotor sections are individually keyed to a rotor shaft such that, in a resting position, the rotor sections are circumferentially shifted (“clocked”) with respect to each to mitigate effects of harmonic feedback, torsional flexibility and the like. In one embodiment, a system includes an electric drive, and an ESP coupled to it by a power cable. The ESP motor has a rotor in which multiple permanent-magnet rotor sections are mounted to a shaft. Within each rotor section, permanent magnets are positioned in two or more axially aligned rows. Adjacent rotor sections are clocked with respect to each other so that, in operation, the rows of permanent magnets in the different rotor sections are positioned to counter the harmonic feedback or to use torsional deflection to equalize torque contributions from the different rotor sections.