公开(公告)号：US5299092A

公开(公告)日：1994-03-29

申请号：US886859

申请日：1992-05-22

Applicant: Akihiro Yaguchi ,  Asao Nishimura ,  Makoto Kitano ,  Ichiro Anjoh ,  Junichi Arita

Inventor： Akihiro Yaguchi ,  Asao Nishimura ,  Makoto Kitano ,  Ichiro Anjoh ,  Junichi Arita

IPC: H01L25/18 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07 ,  H05K7/00 ,  H01L23/28

CPC classification number: H01L23/49575 ,  H01L23/4951 ,  H01L23/49551 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/1815

Abstract: A plastic sealed type semiconductor apparatus includes at least two semiconductor devices which are disposed with a space therebetween in such a manner that circuit forming surfaces oppose each other, and an electric signal lead which is adhered to each of the circuit forming surfaces with an insulating member provided therebetween for electric insulation and which is electrically connected to the semiconductor device by a thin metal wire. The semiconductor devices and the electric signal leads are sealed with a resin in a state where the electric signal leads are laid on top of one another to form a plastic package. The overlaid portion of the electric signal leads has a surface contact portion of the leads and a resin providing portion. The resin providing portion is a recessed portion which is formed when the resin is molded in such a manner that it passes through the surface contact portion of the leads in the lateral direction thereof. The resin providing portion prevents entry of water or moisture and thus eliminates corrosion or breakage of the electric interconnections formed on the circuit forming surface of the semiconductor device or thin metal wires. Thus, the reliability of the semiconductor apparatus is improved.

Abstract translation: 一种塑料密封型半导体装置，包括至少两个半导体器件，它们以彼此相对的电路形成表面的方式设置有它们之间的空间;以及电信号引线，其中每个电路形成表面被绝缘部件 设置在其间用于电绝缘，并且通过细金属线电连接到半导体器件。 半导体器件和电信号引线在电信号引线彼此叠置的状态下用树脂密封以形成塑料封装。 电信号引线的重叠部分具有引线的表面接触部分和树脂提供部分。 树脂提供部分是当树脂以其横向穿过引线的表面接触部分的方式成型时形成的凹部。 树脂提供部分防止水或湿气进入，从而消除在半导体器件或薄金属线的电路形成表面上形成的电互连的腐蚀或断裂。 因此，提高了半导体装置的可靠性。

公开(公告)号：US5295045A

公开(公告)日：1994-03-15

申请号：US791551

申请日：1991-11-14

Applicant: Makoto Kitano ,  Asao Nishimura ,  Akihiro Yaguchi ,  Nae Yoneda ,  Maya Obata ,  Ryuji Kohno ,  Mitsuaki Haneda

Inventor： Makoto Kitano ,  Asao Nishimura ,  Akihiro Yaguchi ,  Nae Yoneda ,  Maya Obata ,  Ryuji Kohno ,  Mitsuaki Haneda

IPC: H01L23/28 ,  H01L23/495 ,  H01L23/50 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K5/02

CPC classification number: H01L23/49575 ,  H01L23/4951 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041

Abstract: A plastic-molded-type semiconductor device having a high degree of integration encases a plurality of semiconductor chips in a package unit with each chip situated perpendicular to the substrate for mounting. On a surface of each chip containing circuits or on a reverse surface of the same, a lead frame is attached with an insulating material interposed therebetween. The chip and lead frame are connected with each other by using wire. The lead frame is arranged perpendicularly to another lead frame provided in parallel and connected therewith by welding. A printed circuit board may be used in place of said latter lead frame. By arranging the chips in projections made of resin, the thermal resistance of the semiconductor device is decreased. The present invention is particularly effective for a memory IC.

Abstract translation: 具有高集成度的塑料模制型半导体器件将多个半导体芯片封装在封装单元中，每个芯片垂直于衬底设置用于安装。 在每个芯片容纳电路的表面上或其背面上，引线框架之间插入绝缘材料。 芯片和引线框架通过电线相互连接。 引线框架垂直布置成并联设置的另一引线框架，通过焊接与引线框架相连接。 可以使用印刷电路板代替所述后置引线框架。 通过将芯片布置在由树脂制成的突起中，半导体器件的热阻降低。 本发明对存储器IC特别有效。

公开(公告)号：US5287284A

公开(公告)日：1994-02-15

申请号：US792160

申请日：1991-11-14

Applicant: Kazuhiro Sugino ,  Shingo Akasaka ,  Hiroko Imanishi ,  Junichi Saeki ,  Kunihiko Nishi ,  Asao Nishimura

Inventor： Kazuhiro Sugino ,  Shingo Akasaka ,  Hiroko Imanishi ,  Junichi Saeki ,  Kunihiko Nishi ,  Asao Nishimura

IPC: G06F17/50 ,  G06Q10/06 ,  G06Q10/08 ,  G06F15/46

CPC classification number: G06Q10/06 ,  G06F17/50 ,  G06Q10/087

Abstract: A product specification complex analysis system is provided which inputs product specifications of an external form and materials, design parameters determined by analysis and evaluation in the specifications, the range of the change of the parameters and a plurality of items of estimates as external input data, calls out and executes an evaluation program corresponding to each item of the estimates and stored in advance, from a group of evaluation programs whenever the item of the estimates is renewed, in order to sequentially evaluate the product specifications for each item of the estimates, determines the fluctuation of analysis results with respect to the change of the design parameters within designated ranges of changes, evaluates trade-off between the analysis results by changing the design parameters from the analysis results corresponding to the items of the estimates so as to make maximal evaluation values in an evaluation formula as an estimate function with weights comprising each of these analysis results, and can thus obtain optimum design parameters.

Abstract translation: 提供了一种产品规格复杂分析系统，其输入外部形式和材料的产品规格，通过规格中的分析和评估确定的设计参数，参数变化的范围和多个估计项作为外部输入数据， 呼叫并执行与估计的每个项目相对应的评估程序，并且每当估计的项目被更新时，从一组评估程序预先存储，以便依次评估估计的每个项目的产品规格，确定 关于设计参数在指定变化范围内变化的分析结果的波动，通过从与估计项目相对应的分析结果中改变设计参数来评估分析结果之间的权衡，以便进行最大评估 评估公式中的值作为具有权重的估计函数 分析这些分析结果，从而获得最佳的设计参数。

公开(公告)号：US5159434A

公开(公告)日：1992-10-27

申请号：US649712

申请日：1991-02-01

Applicant: Ryuji Kohno ,  Makoto Kitano ,  Asao Nishimura ,  Akihiro Yaguchi ,  Sueo Kawai

Inventor： Ryuji Kohno ,  Makoto Kitano ,  Asao Nishimura ,  Akihiro Yaguchi ,  Sueo Kawai

IPC: H01L21/60 ,  H01L23/495

CPC classification number: H01L24/49 ,  H01L23/49503 ,  H01L23/49531 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19107

Abstract: An encapsulated semiconductor device has a chip, a chip pad having through holes and also conducting patterns corresponding to an electrode pad of the chip, and leads. An arbitrary external terminal arrangement is obtained by combining a wire bonding operation between the conduting pattern and lead. Wire bonding is advantageously performed between the leads and electrode pads of the semiconductor chip arranged at arbitrary positions. The degree of freedom in designing areas of the chips and also a printed circuit board is improved so that a high packaging density is achieved and furthermore the printed circuit board is made compact.

Abstract translation: 封装的半导体器件具有芯片，具有通孔的芯片焊盘以及与芯片的电极焊盘相对应的导电图案和引线。 通过组合凹凸图案和导线之间的引线键合操作来获得任意的外部端子布置。 有利地，在布置在任意位置的半导体芯片的引线和电极焊盘之间进行引线接合。 提高了芯片的设计自由度和印刷电路板的自由度，从而实现了高的封装密度，并且印刷电路板的结构紧凑。

公开(公告)号：US4987474A

公开(公告)日：1991-01-22

申请号：US536932

申请日：1990-06-12

Applicant: Toshihiro Yasuhara ,  Masachika Masuda ,  Asao Nishimura ,  Naozumi Hatada ,  Sueo Kawai ,  Makoto Kitano ,  Hideo Miura ,  Akihiro Yaguchi ,  Gen Murakami

Inventor： Toshihiro Yasuhara ,  Masachika Masuda ,  Asao Nishimura ,  Naozumi Hatada ,  Sueo Kawai ,  Makoto Kitano ,  Hideo Miura ,  Akihiro Yaguchi ,  Gen Murakami

IPC: H01L23/495

CPC classification number: H01L24/32 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49558 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351

Abstract: In a tabless lead frame wherein a space for laying inner leads is sufficiently secured when a lengthened and enlarged semiconductor pellet is placed or set in a resin-molding package, through holes are provided in leads for the purpose of increasing the occupation area ratio of a resin portion. Furthermore, each of the leads corresponding to the lower surface of the pellet is branched into a plurality of portions in the widthwise direction thereof in order to reduce a stress. Further, in an insulating sheet which is interposed between the leads and the pellet, the dimension of the shorter lateral sides thereof is set smaller than that of the shorter lateral sides of the pellet in order to prevent cracks from occurring at the end part of the insulating sheet.

Abstract translation: 在放置或放置在树脂成型包装体中的放大或放大的半导体芯片时，用于放置内部引线的空间被充分地固定的无引线框架中，为了增加占空比的目的，提供通孔 树脂部分。 此外，与颗粒的下表面相对应的每个引线在其宽度方向上分支成多个部分，以便减小应力。 此外，在介于引线和芯片之间的绝缘片中，其较短侧面的尺寸被设定为小于颗粒的较短侧面的尺寸，以防止在端部的端部发生裂纹 绝缘片。

公开(公告)号：US07388295B2

公开(公告)日：2008-06-17

申请号：US11350919

申请日：2006-02-10

Applicant: Atsushi Kazama ,  Akihiro Yaguchi ,  Hideo Miura ,  Asao Nishimura

Inventor： Atsushi Kazama ,  Akihiro Yaguchi ,  Hideo Miura ,  Asao Nishimura

IPC: H01L23/48

CPC classification number: H01L23/3157 ,  H01L23/3114 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The distance between farthest ones of external terminal positioned at an outermost end portions of said second semiconductor chip is smaller than that of the first semiconductor chip.

Abstract translation: 多芯片模块具有至少两个半导体芯片。 每个半导体芯片具有半导体芯片的芯片电极，用于与芯片电极电连接的导电互连，用于与互连电连接的导电焊盘，设置在焊盘上的外部端子以及介于两者之间的应力松弛层 土地和半导体芯片。 半导体芯片通过外部端子放置在安装板上。 位于所述第二半导体芯片的最外端部的最外侧端子之间的距离小于第一半导体芯片的距离。

公开(公告)号：US07102221B2

公开(公告)日：2006-09-05

申请号：US10326149

申请日：2002-12-23

Applicant: Toshio Miyamoto ,  Asao Nishimura ,  Toshio Sugano

Inventor： Toshio Miyamoto ,  Asao Nishimura ,  Toshio Sugano

IPC: H01L23/52 ,  H01R9/00

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/5386 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2225/1005 ,  H01L2225/107 ,  H01L2924/01046 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10674 ,  H05K2201/10689 ,  H05K2203/1572 ,  Y02P70/611

Abstract: The invention is intended to increase the density for mounting the semiconductor chips on a memory-module, to increase the capacity of the memory-module, and to realize the memory-module capable of coping with high-speed buses. The memory-module comprises a plurality of WPPs having protruded terminals as external terminals and wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes of semiconductor chips, TSOPs having semiconductor chips, outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips, and a module board supporting the WPPs and the TSOPs, wherein the WPPs and the TSOPs are mounted by the simultaneous reflowing in a mixed manner on the module board.

Abstract translation: 本发明旨在增加用于将半导体芯片安装在存储器模块上的密度，以增加存储器模块的容量，并实现能够应付高速总线的存储器模块。 存储模块包括具有作为外部端子的突出端子的多个WPP和用于在突出端子之间扩展间距的布线部分比半导体芯片的接合电极，具有半导体芯片的TSOP，作为外部端子的外部引线 并且通过电连接到半导体芯片的接合电极的外引线和支撑WPP和TSOP的模块板安装，其中WPP和TSOP通过以混合方式同时回流在 模块板。

公开(公告)号：US06946327B2

公开(公告)日：2005-09-20

申请号：US10771471

申请日：2004-02-05

Applicant: Toshio Miyamoto ,  Ichiro Anjo ,  Asao Nishimura ,  Mitsuaki Katagiri ,  Yuji Shirai ,  Yoshihide Yamaguchi

Inventor： Toshio Miyamoto ,  Ichiro Anjo ,  Asao Nishimura ,  Mitsuaki Katagiri ,  Yuji Shirai ,  Yoshihide Yamaguchi

IPC: H01L21/3205 ,  H01L21/312 ,  H01L21/66 ,  H01L21/822 ,  H01L23/12 ,  H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L23/538 ,  H01L27/04 ,  H01L21/44

CPC classification number: H01L22/22 ,  H01L23/3114 ,  H01L23/5382 ,  H01L24/13 ,  H01L2223/54406 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/11 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2224/05171

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Abstract translation: 半导体集成电路器件包括半导体衬底，形成在半导体衬底的一个主表面上并构成具有多个功能或多个特性的集成电路的电路元件，连接到集成电路的内部连接端子，用于 选择所述集成电路中的多种功能或特性之一，覆盖所述内部连接端子以使得内部连接端子被选择性地暴露的绝缘层和布置在所述绝缘层上的外部连接端子。 通过内部连接端子和外部连接端子之间的连接状态来选择多个功能中的一个或多个特性之一。

公开(公告)号：US20050200019A1

公开(公告)日：2005-09-15

申请号：US11116209

申请日：2005-04-28

Applicant: Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masnori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Hiroshi Koyama ,  Akira Nagai ,  Masahiko Ogino

Inventor： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masnori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Hiroshi Koyama ,  Akira Nagai ,  Masahiko Ogino

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/48 ,  H01L21/44

CPC classification number: H01L24/50 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/50 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

Abstract translation: 半导体器件包括形成有连接端子的半导体芯片，插入在芯片的主表面之间的弹性结构和形成有连接到连接端子的布线的布线基板，以及连接到连接端子的另一端的凸起电极 布线。 连接端子可以在芯片主表面的中心部分或周边部分，并且弹性结构和布线基板都不设置在连接端子的位置处。 树脂体至少密封连接端子和暴露的布线的第一端（引线）。 在连接端子位于芯片主表面的周边部分的方案中，布线基板突出超过布置有连接端子的芯片边界，并且树脂体形状被布线基板的突出部分限制 。

公开(公告)号：US06930388B2

公开(公告)日：2005-08-16

申请号：US09811401

申请日：2001-03-20

Applicant: Yoshihide Yamaguchi ,  Hiroyuki Tenmei ,  Kosuke Inoue ,  Noriyuki Oroku ,  Hiroshi Hozoji ,  Shigeharu Tsunoda ,  Naoya Kanda ,  Madoka Minagawa ,  Ichiro Anjo ,  Asao Nishimura ,  Kenji Ujiie ,  Akira Yajima

Inventor： Yoshihide Yamaguchi ,  Hiroyuki Tenmei ,  Kosuke Inoue ,  Noriyuki Oroku ,  Hiroshi Hozoji ,  Shigeharu Tsunoda ,  Naoya Kanda ,  Madoka Minagawa ,  Ichiro Anjo ,  Asao Nishimura ,  Kenji Ujiie ,  Akira Yajima

IPC: H01L23/29 ,  H01L21/56 ,  H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L23/3171 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/01034 ,  H01L2924/00014

Abstract: A semiconductor device is provided which enables a flip chip connection without use of underfill. The semiconductor device includes a semiconductor element having circuit electrodes and a circuit surface coated with a protecting film. A stress relaxation layer is provided by coating a cured thermoplastic resin onto the protecting film of the circuit surface in a manner which leaves the circuit electrodes exposed and curing it and having an inclination in the edge portion thereof. A wiring layer with wirings is connected to each of the circuit electrodes and disposed so as to make an electrical connection from the circuit electrodes, via the edge portion of the stress relaxation layer, and to a desired portion on the surface of the stress relaxation layer. A protecting film is provided thereon, and an external connection terminal is also provided.

Abstract translation: 提供一种半导体器件，其能够在不使用底部填充物的情况下实现倒装芯片连接。 半导体器件包括具有电路电极的半导体元件和涂有保护膜的电路表面。 通过将固化的热塑性树脂以使电路电极暴露并固化并且在其边缘部分具有倾斜的方式将固化的热塑性树脂涂覆到电路表面的保护膜上来提供应力松弛层。 具有布线的布线层连接到每个电路电极，并布置成经由应力松弛层的边缘部分和电路电极的电连接到应力松弛层的表面上的期望部分 。 在其上设置有保护膜，并且还设置有外部连接端子。