HIERARCHICAL PACKET PROCESS APPARATUS AND METHOD
    52.
    发明申请
    HIERARCHICAL PACKET PROCESS APPARATUS AND METHOD 审中-公开
    分层分组过程设备和方法

    公开(公告)号:US20100158009A1

    公开(公告)日:2010-06-24

    申请号:US12626009

    申请日:2009-11-25

    Abstract: Provided is a hierarchical packet processing apparatus and method. In one general aspect, a packet is analyzed, divided into an upper layer and a lower layer. It is determined whether a property of the packet to be analyzed has been already analyzed or has to be re-analyzed with respect to each of the upper and lower layers of the packet. Therefore, deep packet inspection is performed only when it is required, and thus assurance of quality of service (QoS) during packet processing can be achieved, as well as reduced waste of resources.

    Abstract translation: 提供了一种分层分组处理装置和方法。 在一个一般方面,分析分组,分成上层和下层。 确定要分析的分组的属性是否已经被分析或者必须相对于分组的每个上层和下层被重新分析。 因此,只有在需要时才进行深度包检测,从而可以实现数据包处理期间的服务质量(QoS)保证,减少资源浪费。

    TIMESTAMPING METHOD AND APPARATUS FOR PRECISE NETWORK SYNCHRONIZATION
    53.
    发明申请
    TIMESTAMPING METHOD AND APPARATUS FOR PRECISE NETWORK SYNCHRONIZATION 有权
    用于精确网络同步的计时方法和装置

    公开(公告)号:US20100074383A1

    公开(公告)日:2010-03-25

    申请号:US12423090

    申请日:2009-04-14

    CPC classification number: H04J3/0667 H04J3/0697

    Abstract: A timestamping apparatus for network synchronization includes a recovery unit and a timestamping unit. The recovery unit extracts a recovery clock operating at an operation frequency of a transmission terminal from a sync signal received from the transmission terminal. The timestamping unit measures a timestamp value of an arrival time of the sync signal by measuring a phase difference between the recovery clock and a local clock of a receiving terminal.

    Abstract translation: 用于网络同步的时间戳装置包括恢复单元和时间戳单元。 恢复单元从从发送终端接收到的同步信号中提取在发送终端的操作频率下工作的恢复时钟。 时间戳单元通过测量恢复时钟和接收终端的本地时钟之间的相位差来测量同步信号的到达时间的时间戳值。

    Method for processing subscriber packet using subscriber identification tag
    54.
    发明申请
    Method for processing subscriber packet using subscriber identification tag 审中-公开
    使用用户识别标签处理用户分组的方法

    公开(公告)号:US20070053353A1

    公开(公告)日:2007-03-08

    申请号:US11321191

    申请日:2005-12-29

    Abstract: A method of classifying packets by a subscriber and processing classified packet to provide fairness to subscribers is provided. In order to classify the packets by the subscriber, a subscriber identification tag is inserted into a predetermined portion of an Ethernet frame and the packets are classified using the subscriber identification tag. The classified packets are processed based on the classifying result. Accordingly, an intermediate node not directly connected to the subscriber can classify the packets by the subscriber even in an uncontrollably expanded subscriber network. Therefore, the subscriber network is simply and effectively managed while providing the fairness to the subscriber in processing packets and allocating bandwidth.

    Abstract translation: 提供了一种由用户分类分组并处理分类分组以向用户提供公平性的方法。 为了对用户对分组进行分类,将用户识别标签插入到以太网帧的预定部分中,并且使用用户识别标签对分组进行分类。 根据分类结果处理分类数据包。 因此,即使在不受控制地扩展的用户网络中,直接连接到用户的中间节点也可以由用户对分组进行分类。 因此,用户网络简单有效地被管理,同时在处理分组和分配带宽时向用户提供公平性。

    Efficient switching device and method for fabricating the same using multiple shared memories
    55.
    发明申请
    Efficient switching device and method for fabricating the same using multiple shared memories 失效
    高效开关器件及其制造方法使用多个共享存储器

    公开(公告)号:US20060146851A1

    公开(公告)日:2006-07-06

    申请号:US11292983

    申请日:2005-12-01

    CPC classification number: H04L49/3036 H04L49/25 H04L49/3072

    Abstract: An efficient switching device and a method for fabricating the same using multiple shared memories are provided. The switching device includes: an output time determination unit to determine an output time to an output port; an output time administration unit to administer a possible data output time for each output port; a memory bank selection unit to select a memory bank with an empty data output time position; a memory bank utilization information administration unit to administer utilization information per output time; a connection unit to deliver transmission data to an output time position; a shared memory unit to store the data in the output time position, to administer dispersed shared memory banks according to an output time, and to read and output transmission data; and an output port connection unit receiving output data to read and transmit output port information of the data to a corresponding output port.

    Abstract translation: 提供了一种有效的开关器件及其使用多个共享存储器的制造方法。 开关装置包括:输出时间确定单元,用于确定到输出端口的输出时间; 输出时间管理单元,用于管理每个输出端口的可能的数据输出时间; 存储器选择单元,用于选择具有空数据输出时间位置的存储体; 存储库利用信息管理单元,用于管理每个输出时间的利用信息; 连接单元,用于将传输数据传送到输出时间位置; 共享存储器单元,用于将数据存储在输出时间位置,以根据输出时间来管理分散的共享存储体,并读取和输出传输数据; 以及输出端口连接单元,其接收输出数据以将数据的输出端口信息读取并发送到相应的输出端口。

    Apparatus for changing MAC address to identify subscriber and method thereof
    56.
    发明申请
    Apparatus for changing MAC address to identify subscriber and method thereof 有权
    用于改变MAC地址以识别用户的装置及其方法

    公开(公告)号:US20060126622A1

    公开(公告)日:2006-06-15

    申请号:US11302604

    申请日:2005-12-13

    Abstract: Provided is an apparatus for changing Media Access Control (MAC) address, which is a conventional subscriber hardware identification address for identifying each subscriber, and a method thereof. The MAC address changing apparatus includes a frame receiving block for determining whether to change a source MAC address; a switch controlling block for controlling a switch; a change MAC address generating block for changing the source MAC address of the received frame; a change MAC address storing block for storing information of the change MAC address and the source MAC address corresponding thereto; a MAC address forwarding and lookup block for extracting output port information; a MAC address replacing block for forming an output frame by replacing the source MAC address; a MAC address storing block for storing a MAC address; and a frame transmitting block for transmitting the output frame.

    Abstract translation: 提供了一种用于改变媒体访问控制(MAC)地址的装置,其是用于识别每个订户的常规用户硬件标识地址及其方法。 MAC地址改变装置包括用于确定是否改变源MAC地址的帧接收块; 用于控制开关的开关控制块; 改变MAC地址生成块,用于改变接收到的帧的源MAC地址; 更改MAC地址存储块,用于存储与其对应的改变MAC地址和源MAC地址的信息; 用于提取输出端口信息的MAC地址转发和查找块; 用于通过替换源MAC地址来形成输出帧的MAC地址替换块; 用于存储MAC地址的MAC地址存储块; 以及用于发送输出帧的帧发送块。

    Digital phase alignment apparatus in consideration of metastability
    57.
    发明授权
    Digital phase alignment apparatus in consideration of metastability 失效
    考虑到亚稳态的数字相位对准装置

    公开(公告)号:US6031886A

    公开(公告)日:2000-02-29

    申请号:US137747

    申请日:1998-08-21

    CPC classification number: H04L7/0338

    Abstract: The present invention provides a digital phase alignment which to select the clock whose the transition is occured in the close vicinity of a center of the input data unit interval, the rising transition or falling transition of data are detected, as a result, to generate the synthetic clock retiming data upon detecting the transition of data having a random bit column, the retiming clock is reached in the center of eye pattern of data, compared with a single directional transition is detected.

    Abstract translation: 本发明提供一种数字相位对准,其选择在输入数据单位间隔的中心附近发生转变的时钟,检测数据的上升转变或下降转换,结果产生 在检测到具有随机位列的数据的转变时的合成时钟重新定时数据,与检测到单个方向转换相比,在眼图数据的中心达到重新定时时钟。

    Cyclic line coding apparatus for error detection and frame recovery
    58.
    发明授权
    Cyclic line coding apparatus for error detection and frame recovery 失效
    用于错误检测和帧恢复的循环线编码装置

    公开(公告)号:US5703882A

    公开(公告)日:1997-12-30

    申请号:US571077

    申请日:1995-12-12

    Abstract: A modified cyclic line coding apparatus for error detection and frame recovery which generates a n-bit modified cyclic cord-word by use of k redundancy bits and partially scrambles the cyclic redundancy check bits using periodic scramble bits. The apparatus includes a transmitter including a modified cyclic redundancy generator unit for generating redundancy bits, a variable period sampled scrambler unit for partially scrambling the redundancy bits, a timing control unit for generating a timing signal, and a multiplexer unit for multiplexing input cell data in accordance with the timing signal. The apparatus also includes a receiver including a modified cyclic redundancy checker unit for outputting a block synchronization signal and sample bits when a block synchronization is detected, while outputting a synchronization error signal when no block synchronization is detected, a variable period sampled descrambler unit for generating descramble bits in accordance with the sample bits, a timing recovering unit for generating a timing signal, and a demultiplexer unit for demultiplexing the cell data in accordance with the timing signal. The apparatus can use various cell sizes, can stably receive the user information of cell data and can achieve an easy bit timing detection.

    Abstract translation: 一种用于错误检测和帧恢复的修改的循环线编码装置,其通过使用k个冗余比特生成n位修改的循环线字,并且使用周期性扰频比特部分地对循环冗余校验位进行加扰。 该装置包括:发射机,包括用于产生冗余比特的修改的循环冗余发生器单元,用于对冗余比特进行部分加扰的可变周期采样扰频单元,用于产生定时信号的定时控制单元,以及用于复用输入单元数据的多路复用器单元 根据定时信号。 该装置还包括一个接收机,包括一个修改的循环冗余校验器单元,用于当检测到块同步时输出块同步信号和采样位,同时在没有检测到块同步时输出同步误差信号;可变周期采样解扰器单元,用于产生 根据采样位的解扰位,用于产生定时信号的定时恢复单元和用于根据定时信号对单元数据解复用的解复用器单元。 该装置可以使用各种小区大小,可以稳定地接收小区数据的用户信息,并且可以实现容易的比特定时检测。

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