Abstract:
A parallel processing-based time synchronization apparatus is disclosed. The time synchronization apparatus employs a double-filter structure based on parallel processing, thereby providing more precise and reliable time synchronization between a master device and a slave device.
Abstract:
Provided is a hierarchical packet processing apparatus and method. In one general aspect, a packet is analyzed, divided into an upper layer and a lower layer. It is determined whether a property of the packet to be analyzed has been already analyzed or has to be re-analyzed with respect to each of the upper and lower layers of the packet. Therefore, deep packet inspection is performed only when it is required, and thus assurance of quality of service (QoS) during packet processing can be achieved, as well as reduced waste of resources.
Abstract:
A timestamping apparatus for network synchronization includes a recovery unit and a timestamping unit. The recovery unit extracts a recovery clock operating at an operation frequency of a transmission terminal from a sync signal received from the transmission terminal. The timestamping unit measures a timestamp value of an arrival time of the sync signal by measuring a phase difference between the recovery clock and a local clock of a receiving terminal.
Abstract:
A method of classifying packets by a subscriber and processing classified packet to provide fairness to subscribers is provided. In order to classify the packets by the subscriber, a subscriber identification tag is inserted into a predetermined portion of an Ethernet frame and the packets are classified using the subscriber identification tag. The classified packets are processed based on the classifying result. Accordingly, an intermediate node not directly connected to the subscriber can classify the packets by the subscriber even in an uncontrollably expanded subscriber network. Therefore, the subscriber network is simply and effectively managed while providing the fairness to the subscriber in processing packets and allocating bandwidth.
Abstract:
An efficient switching device and a method for fabricating the same using multiple shared memories are provided. The switching device includes: an output time determination unit to determine an output time to an output port; an output time administration unit to administer a possible data output time for each output port; a memory bank selection unit to select a memory bank with an empty data output time position; a memory bank utilization information administration unit to administer utilization information per output time; a connection unit to deliver transmission data to an output time position; a shared memory unit to store the data in the output time position, to administer dispersed shared memory banks according to an output time, and to read and output transmission data; and an output port connection unit receiving output data to read and transmit output port information of the data to a corresponding output port.
Abstract:
Provided is an apparatus for changing Media Access Control (MAC) address, which is a conventional subscriber hardware identification address for identifying each subscriber, and a method thereof. The MAC address changing apparatus includes a frame receiving block for determining whether to change a source MAC address; a switch controlling block for controlling a switch; a change MAC address generating block for changing the source MAC address of the received frame; a change MAC address storing block for storing information of the change MAC address and the source MAC address corresponding thereto; a MAC address forwarding and lookup block for extracting output port information; a MAC address replacing block for forming an output frame by replacing the source MAC address; a MAC address storing block for storing a MAC address; and a frame transmitting block for transmitting the output frame.
Abstract:
The present invention provides a digital phase alignment which to select the clock whose the transition is occured in the close vicinity of a center of the input data unit interval, the rising transition or falling transition of data are detected, as a result, to generate the synthetic clock retiming data upon detecting the transition of data having a random bit column, the retiming clock is reached in the center of eye pattern of data, compared with a single directional transition is detected.
Abstract:
A modified cyclic line coding apparatus for error detection and frame recovery which generates a n-bit modified cyclic cord-word by use of k redundancy bits and partially scrambles the cyclic redundancy check bits using periodic scramble bits. The apparatus includes a transmitter including a modified cyclic redundancy generator unit for generating redundancy bits, a variable period sampled scrambler unit for partially scrambling the redundancy bits, a timing control unit for generating a timing signal, and a multiplexer unit for multiplexing input cell data in accordance with the timing signal. The apparatus also includes a receiver including a modified cyclic redundancy checker unit for outputting a block synchronization signal and sample bits when a block synchronization is detected, while outputting a synchronization error signal when no block synchronization is detected, a variable period sampled descrambler unit for generating descramble bits in accordance with the sample bits, a timing recovering unit for generating a timing signal, and a demultiplexer unit for demultiplexing the cell data in accordance with the timing signal. The apparatus can use various cell sizes, can stably receive the user information of cell data and can achieve an easy bit timing detection.