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    Strained-channel semiconductor structure and method of fabricating the same
    51.
    发明授权
    Strained-channel semiconductor structure and method of fabricating the same 有权
    应变通道半导体结构及其制造方法

    公开(公告)号：US07078742B2

    公开(公告)日：2006-07-18

    申请号：US10655255

    申请日：2003-09-04

    Applicant: Chun-Chieh Lin ,  Yee-Chia Yeo

    Inventor： Chun-Chieh Lin ,  Yee-Chia Yeo

    IPC: H01L31/0312 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/78

    CPC classification number: H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7848 ,  Y10S438/938

    Abstract: A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region A pair of source/drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source/drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.

    Abstract translation: 应变通道半导体结构及其制造方法。 应变通道半导体结构包括由具有第一自然晶格常数的第一半导体材料构成的衬底。 沟道区设置在衬底中，并且栅堆叠设置在应变沟道区上方，一对源极/漏极区相对地设置在与沟道区相邻的衬底中，其中源/漏区中的每一个包括晶格 - 错配区域包括具有第二自然晶格常数而不是第一自然晶格常数的第二半导体材料，对应于栅极堆叠的内侧和外侧，并且至少一个外侧横向接触基板的第一半导体材料。

    A Recessed Polysilicon Gate Structure for a Strained Silicon MOSFET Device
    52.
    发明申请
    A Recessed Polysilicon Gate Structure for a Strained Silicon MOSFET Device 有权
    用于应变硅MOSFET器件的嵌入式多晶硅栅极结构

    公开(公告)号：US20060009001A1

    公开(公告)日：2006-01-12

    申请号：US10864952

    申请日：2004-06-10

    Applicant: Yi-Chun Huang ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Lawrence Sheu ,  Huan-Jan Tao ,  Chih-Hsin Ko ,  Chun-Chieh Lin

    Inventor： Yi-Chun Huang ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Lawrence Sheu ,  Huan-Jan Tao ,  Chih-Hsin Ko ,  Chun-Chieh Lin

    IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/76

    CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

    Abstract: Abstract of the Disclosure A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portion reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

    Abstract translation: 发明内容已经开发出通过使用相邻和周围的硅 - 锗形状在应变硅层中形成用于MOSFET器件的沟道区的方法。 该方法同时形成导电栅极结构的顶部中的凹部并且在半导体衬底的不被栅极结构占据的部分中，或者位于导电栅极结构的侧面上的虚设间隔物。 选择性限定的凹槽将用于随后容纳硅锗形状，其中硅 - 锗形状位于半导体衬底的凹陷中，从而诱导期望的应变通道区域。 导电栅极结构和半导体衬底部分的凹陷减少了在合金层的外延生长期间跨越侧壁间隔物表面的硅 - 锗桥接的风险，从而降低了栅极到衬底泄漏或短路的风险。

    Semiconductor device substrate with embedded capacitor
    54.
    发明申请
    Semiconductor device substrate with embedded capacitor 有权
    具有嵌入式电容器的半导体器件衬底

    公开(公告)号：US20060003522A1

    公开(公告)日：2006-01-05

    申请号：US10881372

    申请日：2004-06-30

    Applicant: Chun-Chieh Lin ,  Wen-Chin Lee

    Inventor： Chun-Chieh Lin ,  Wen-Chin Lee

    IPC: H01L21/8234 ,  H01L21/8244 ,  H01L21/8242

    CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/10858 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/55 ,  H01L28/82

    Abstract: A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.

    Abstract translation: 一种用于形成半导体器件的方法，该半导体器件包括具有嵌入式电容器结构的绝缘体上硅（SOI）衬底的DRAM单元结构，包括提供包括上覆的第一电绝缘层的衬底; 在所述第一电绝缘层上形成第一导电层以形成第一电极; 在所述第一电极上形成电容器电介质层; 在所述电容器介电层上形成第二导电层以形成第二电极; 在所述第二电极上形成第二电绝缘层; 以及在所述第二电极上形成单晶硅层以形成包括第一电容器结构的SOI衬底。

    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
    55.
    发明授权
    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement 有权
    应变平衡结构具有拉伸应变硅通道和压缩应变硅 - 锗通道，用于CMOS性能提升

    公开(公告)号：US06955952B2

    公开(公告)日：2005-10-18

    申请号：US10383709

    申请日：2003-03-07

    Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    IPC: H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L31/109

    CPC classification number: H01L29/1054 ,  H01L21/84 ,  H01L27/1203

    Abstract: A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile stain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

    Abstract translation: 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于双轴拉伸污染增强电子迁移率的硅层中。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

    Strained-channel semiconductor structure and method of fabricating the same
    56.
    发明申请
    Strained-channel semiconductor structure and method of fabricating the same 有权
    应变通道半导体结构及其制造方法

    公开(公告)号：US20050184345A1

    公开(公告)日：2005-08-25

    申请号：US10655255

    申请日：2003-09-04

    Applicant: Chun-Chieh Lin ,  Yee-Chia Yeo

    Inventor： Chun-Chieh Lin ,  Yee-Chia Yeo

    IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78

    CPC classification number: H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7848 ,  Y10S438/938

    Abstract: A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region A pair of source/drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source/drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.

    Abstract translation: 应变通道半导体结构及其制造方法。 应变通道半导体结构包括由具有第一自然晶格常数的第一半导体材料构成的衬底。 沟道区设置在衬底中，并且栅堆叠设置在应变沟道区上方，一对源极/漏极区相对地设置在与沟道区相邻的衬底中，其中源/漏区中的每一个包括晶格 - 错配区域包括具有第二自然晶格常数而不是第一自然晶格常数的第二半导体材料，对应于栅极堆叠的内侧和外侧，并且至少一个外侧横向接触基板的第一半导体材料。

    Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer
    58.
    发明授权
    Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer 有权
    使用应变硅锗层的选择性外延的互补金属氧化物半导体晶体管技术

    公开(公告)号：US06703271B2

    公开(公告)日：2004-03-09

    申请号：US10002031

    申请日：2001-11-30

    Applicant: Yee-Chia Yeo ,  Chun Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

    Inventor： Yee-Chia Yeo ,  Chun Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

    IPC: H01L218238

    CPC classification number: H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

    Abstract: A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The composite silicon layer is comprised of a thin, strained SiGe layer sandwiched between selectively grown, undoped silicon layers. The content of Ge in the SiGe layer, between about 20 to 40 weight percent, allows enhanced carrier mobility to exist without creation of silicon defects. A thin silicon dioxide gate insulator is thermally grown from a top portion of the selectively grown silicon layer, located overlying the selectively grown SiGe layer.

    Abstract translation: 已经开发了用于制造具有包含应变SiGe层的沟道区的CMOS器件的工艺。 该工艺的特点是在N阱和P阱区的顶表面上复合硅层的选择性生长。 复合硅层由夹在选择性生长的未掺杂硅层之间的薄的应变SiGe层组成。 SiGe层中Ge的含量在约20至40重量％之间，允许存在增加的载流子迁移率而不产生硅缺陷。 薄的二氧化硅栅极绝缘体从选择性地生长的硅层的顶部热生长，位于覆盖选择性生长的SiGe层上。

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