公开(公告)号：US5536674A

公开(公告)日：1996-07-16

申请号：US345891

申请日：1994-11-28

申请人： Yasunobu Kosa ,  Howard C. Kirsch ,  Thomas F. McNelly ,  Frank K. Baker

发明人： Yasunobu Kosa ,  Howard C. Kirsch ,  Thomas F. McNelly ,  Frank K. Baker

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11

摘要： A static-random-access memory cell comprising floating node capacitors is disclosed. In one embodiment, the storage nodes acts as the first plates for the floating node capacitors, and a conductive member acts as the second plates for the floating node capacitors. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cell. In another embodiment, a conductive member acts as the second plates of a plurality of memory cells. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cells. Processes for forming the memory cells is also disclosed.

摘要翻译： 公开了一种包括浮动节点电容器的静态随机存取存储器单元。 在一个实施例中，存储节点用作浮动节点电容器的第一板，并且导电构件用作浮动节点电容器的第二板。 导电构件还将第二板电连接在一起，但不与存储单元的其它部分电连接。 在另一个实施例中，导电构件用作多个存储单元的第二板。 导电构件还将第二板电连接在一起，但不与存储单元的其它部分电连接。 还公开了用于形成存储单元的工艺。

公开(公告)号：US5445107A

公开(公告)日：1995-08-29

申请号：US155607

申请日：1993-11-22

申请人： Scott S. Roth ,  Howard C. Kirsch

发明人： Scott S. Roth ,  Howard C. Kirsch

IPC分类号： C30B1/02

CPC分类号： H01L27/1203 ,  C30B1/023 ,  C30B29/06 ,  H01L21/84

摘要： A silicon-on insulator film (38) is formed by solid phase epitaxial re-growth. A layer of amorphous silicon (36) is formed such that it is only in direct contact with an underlying portion of a silicon substrate (12). The layer of amorphous silicon (36) is subsequently annealed to form a monocrystalline layer of epitaxial silicon (38). Because the amorphous silicon layer (36) is in contact with only the silicon substrate (12), during the re-growth process, the resulting epitaxial layer (38) is formed with a reduced number of crystal defects. The resulting epitaxial silicon layer (38) may then be used to form semiconductor devices.

摘要翻译： 通过固相外延再生长形成硅上绝缘膜（38）。 形成一层非晶硅（36），使其仅与硅衬底（12）的下部直接接触。 然后将非晶硅层（36）退火以形成外延硅单晶层（38）。 由于非晶硅层（36）仅与硅衬底（12）接触，所以在再生长过程中，所形成的外延层（38）形成数量减少的晶体缺陷。 然后可以使用所得的外延硅层（38）来形成半导体器件。

公开(公告)号：US5416736A

公开(公告)日：1995-05-16

申请号：US279963

申请日：1994-07-25

申请人： Yasunobu Kosa ,  Howard C. Kirsch

发明人： Yasunobu Kosa ,  Howard C. Kirsch

IPC分类号： H01L27/10 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L29/66666 ,  H01L21/26586 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/6675 ,  H01L29/7827 ,  H01L29/7834 ,  Y10S257/904

摘要： The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a static random access memory cell (110) having a vertical n-channel field-effect transistor (116) and a vertical p-channel field-effect transistor (115) and methods of forming them. In one embodiment, a six-transistor static random access memory cell (110) has two pass transistors (111 and 114), which are planar n-channel field-effect transistors, two latch transistors (113 and 116), which are vertical n-channel field-effect transistors with drain regions having graded diffusion junctions (31), and two load transistors (112 and 115), which are vertical p-channel thin-film field-effect transistors having laterally recessed channel regions (92).

摘要翻译： 本公开包括具有横向凹陷沟道区域（92）的垂直场效应晶体管（115），具有渐变扩散结（31）的垂直场效应晶体管（116），具有梯度扩散结（31）的静态随机存取存储单元（110） 垂直n沟道场效应晶体管（116）和垂直p沟道场效应晶体管（115）及其形成方法。 在一个实施例中，六晶体管静态随机存取存储单元（110）具有平面n沟道场效应晶体管的两个通过晶体管（111和114），两个垂直n的晶体管（113和116） 具有分级扩散结（31）的漏极区的沟道场效应晶体管和具有侧向凹陷沟道区（92）的垂直p沟道薄膜场效应晶体管的两个负载晶体管（112和115）。

公开(公告)号：US4679172A

公开(公告)日：1987-07-07

申请号：US738664

申请日：1985-05-28

申请人： Howard C. Kirsch ,  Frank J. Procyk

发明人： Howard C. Kirsch ,  Frank J. Procyk

IPC分类号： G11C11/409 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C11/4094 ,  G11C11/406

摘要： A dynamic memory obtains reduced leakage currents through the access transistors by preventing the low-going column conductors from reaching zero volts for at least a majority of the duration of the active portion of a memory cycle. The low-going conductors are allowed to reach zero volts during the refresh operation. One advantage is a possible increase in the data storage time between required refresh operations. An increase in the refresh interval is especially useful for memory operations wherein a multiplicity of columns are selected for a given row selection. The present technique also addresses the tendency toward increased sub-threshold leakage as field effect transistor thresholds decrease.

摘要翻译： 动态存储器通过防止低位列导体在存储器周期的有效部分的持续时间的至少大部分时间内达到零伏特来获得通过存取晶体管的减小的漏电流。 在刷新操作期间，低导体允许达到零伏特。 一个优点是可能增加所需的刷新操作之间的数据存储时间。 刷新间隔的增加对于对于给定行选择选择多个列的存储器操作特别有用。 本技术还解决了随着场效应晶体管阈值下降而增加的次阈值泄漏的趋势。

公开(公告)号：US4366400A

公开(公告)日：1982-12-28

申请号：US96897

申请日：1979-11-23

申请人： Howard C. Kirsch

发明人： Howard C. Kirsch

IPC分类号： H03K6/02 ,  G11C11/4074 ,  H02M3/07 ,  H03K5/02 ,  H03K17/284 ,  H03K17/687 ,  H03K19/0175 ,  H03K3/353

CPC分类号： G11C11/4074 ,  H02M3/07 ,  H03K5/023

摘要： A delay gate circuit consists of first and second stages which each have two serially connected MOS transistors and of a fifth MOS transistor. The gates of the transistors of the first stage serve as first and second circuit input terminals. The gate of the second transistor of the first stage is connected to the gate of the first transistor of the second stage. An output terminal of the first stage is connected to the gate of the second transistor of the second stage and to the drain of the fifth MOS transistor. An output terminal of the second stage is connected to the gate of the fifth transistor and serves as the output circuit terminal.

公开(公告)号：US4250414A

公开(公告)日：1981-02-10

申请号：US929369

申请日：1978-07-31

申请人： Howard C. Kirsch

发明人： Howard C. Kirsch

IPC分类号： H03K6/02 ,  G11C11/4074 ,  H02M3/07 ,  H03K5/02 ,  H03K17/284 ,  H03K17/687 ,  H03K19/0175 ,  H03K3/00 ,  H02M9/04 ,  H03K17/10

CPC分类号： G11C11/4074 ,  H02M3/07 ,  H03K5/023

摘要： Voltage generator circuitry uses a first capacitor (Q1) that is selectively isolated from an output terminal (26) by a first transistor (Q4). The gate of Q4 is coupled to a circuit terminal (16) which is capacitively coupled via second capacitor (Q5) to the output terminal (20) of a delay gate (28). The first capacitor (Q1) is charged to a potential level near or at that of a power supply (VDD) and then a positive going waveform applied to Q1 causes it to be charged to a potential level above VDD. Terminal 16 is charged by the positive going waveform to a value at or near VDD and then it is increased in potential after the delay time of the delay gate (28). This enables (biases on) Q4 and allows the output terminal (26) to assume a potential level greater than that of VDD.

摘要翻译： 电压发生器电路使用通过第一晶体管（Q4）与输出端子（26）选择性隔离的第一电容器（Q1）。 Q4的栅极耦合到经由第二电容器（Q5）电容耦合到延迟门（28）的输出端子（20）的电路端子（16）。 将第一电容器（Q1）充电到电源（VDD）附近的电位电平，然后施加到Q1的正向波形使其被充电到高于VDD的电位电平。 端子16由正向波形充电到VDD附近或附近的值，然后在延迟门（28）的延迟时间之后其电位增加。 这使得能够（偏置）Q4并且允许输出端子（26）呈现比VDD大的电位电平。

公开(公告)号：US08962401B2

公开(公告)日：2015-02-24

申请号：US13455956

申请日：2012-04-25

申请人： Werner Juengling ,  Howard C. Kirsch

发明人： Werner Juengling ,  Howard C. Kirsch

IPC分类号： H01L21/00 ,  H01L27/108 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10891 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/7855

摘要： A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.

摘要翻译： 提供一种半导体器件，其包括在第一沟槽中形成有鳍状物的第一侧壁上的第一栅极和第二栅极的鳍片，其中第一栅极形成在第二栅极之上。 该器件包括在第二沟槽中形成在鳍片的第二侧壁上的第三栅极和第四栅极，其中第三栅极形成在第四栅极之上。 还包括制造和操作设备的方法。 一种操作方法可以包括偏置第一栅极和第四栅极以产生穿过散热片的电流路径。

公开(公告)号：US20130039132A1

公开(公告)日：2013-02-14

申请号：US13204994

申请日：2011-08-08

申请人： Tae H. Kim ,  Howard C. Kirsch ,  Yu-Wen Huang ,  Mingshiang Wang ,  Todd A. Merritt

发明人： Tae H. Kim ,  Howard C. Kirsch ,  Yu-Wen Huang ,  Mingshiang Wang ,  Todd A. Merritt

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C7/18 ,  G11C8/08

摘要： Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.

摘要翻译： 描述的实施例涉及线路驱动器，例如用于在存储器阵列中提供减小的栅极感应漏极泄漏的线路驱动器。 还公开了线路驱动器的相应的操作方法。

公开(公告)号：US07460430B2

公开(公告)日：2008-12-02

申请号：US11497176

申请日：2006-08-01

申请人： Tae H. Kim ,  Charles L. Ingalls ,  Howard C. Kirsch ,  Jeremy J. Gum

发明人： Tae H. Kim ,  Charles L. Ingalls ,  Howard C. Kirsch ,  Jeremy J. Gum

IPC分类号： G11C8/00

CPC分类号： G11C8/08

摘要： Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak transistor to ground and a strong transistor to ground. By disabling the wordline driver on the wordlines directly adjacent to the active wordlines, a path is provided to drive the coupling noise from the active wordline to ground through the strong transistor.

摘要翻译： 配置为减少存储器阵列中相邻字线之间的耦合噪声的存储器件。 更具体地说，字线驱动器被交错，使得相邻字线由不同行解码器启用的字线驱动器驱动。 每个字线驱动器包括一个微弱的晶体管接地和一个强大的晶体管接地。 通过禁用与​​有源字线直接相邻的字线上的字线驱动器，提供一个路径，以通过强晶体管驱动从有源字线到地的耦合噪声。

公开(公告)号：US07440344B2

公开(公告)日：2008-10-21

申请号：US11732219

申请日：2007-04-03

申请人： Tae H. Kim ,  Michael V. Cordoba ,  Howard C. Kirsch

发明人： Tae H. Kim ,  Michael V. Cordoba ,  Howard C. Kirsch

IPC分类号： G11C7/00

CPC分类号： G11C5/147 ,  G11C16/30 ,  H03K3/356113

摘要： A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control of the flipping of nodes is dependent on gate voltages as opposed to P/N ratios.

摘要翻译： 电压电平转换器提高晶体管的栅极电压，并增加栅极到源极电压，以允许在更宽的电源电压范围内工作。 因此，电压电平转换器中的晶体管的P / N比被增加，并且节点的翻转的控制取决于栅极电压而不是P / N比。