公开(公告)号：US06627387B2

公开(公告)日：2003-09-30

申请号：US09827827

申请日：2001-04-05

申请人： Kevin Hsieh ,  Chih-Yung Lin ,  Chih-Hsiang Hsiao ,  Juan-Yuan Wu ,  Water Lur

发明人： Kevin Hsieh ,  Chih-Yung Lin ,  Chih-Hsiang Hsiao ,  Juan-Yuan Wu ,  Water Lur

IPC分类号： G03F726

CPC分类号： G03F7/091 ,  Y10S430/151

摘要： A method of photolithography. An anti-reflective coating is formed on the conductive layer. An nitrogen plasma treatment is performed. A photo-resist layer is formed and patterned on the anti-reflective coating. The conductive layer is defined. The photo-resist layer is removed. The anti-reflective layer is removed by using phosphoric acid.

公开(公告)号：US06448159B1

公开(公告)日：2002-09-10

申请号：US09692251

申请日：2000-10-19

申请人： Coming Chen ,  Juan-Yuan Wu ,  Water Lur

发明人： Coming Chen ,  Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L2120

CPC分类号： H01L21/31144 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/76229 ,  Y10S438/942

摘要： A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

摘要翻译： 公开了用于形成浅沟槽隔离的化学机械抛光的方法。 提供了具有多个有源区的衬底，包括多个相对较大的有源区和多个相对小的有源区。 该方法包括以下步骤。 首先形成衬底上的氮化硅层。 在活性区域之间形成多个浅沟槽。 在衬底上形成氧化物层，使得浅沟槽被氧化物层填充。 在氧化物层上形成部分反向有源掩模。 部分反射器主动掩模在每个相对较大的有效区域的中心部分具有开口。 开口暴露氧化物层的一部分。 开口至少有一个虚拟图案。 去除每个大的有源区的中心部分的氧化物层，以露出氮化硅层。 去除部分反向主动掩模。 将氧化物层平坦化以暴露氮化硅层。

公开(公告)号：US06337279B1

公开(公告)日：2002-01-08

申请号：US09215061

申请日：1998-12-17

申请人： Chao-Yuan Huang ,  Juan-Yuan Wu ,  Water Lur

发明人： Chao-Yuan Huang ,  Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L21302

CPC分类号： H01L21/76224 ,  H01L21/31053

摘要： A method of fabricating a shallow trench isolation in semiconductor substrate comprises a densification process after performing chemical-mechanical polishing on an isolation plug. Thus, the isolation plug can prevent micro-scratches from forming deep scratches. Therefore, shorts arising from the micro-scratches do not happen.

摘要翻译： 在半导体衬底中制造浅沟槽隔离的方法包括在隔离插头上进行化学机械抛光之后的致密化过程。 因此，隔离塞可以防止微划痕形成深划痕。 因此，微刮痕产生的短路不会发生。

公开(公告)号：US06319814B1

公开(公告)日：2001-11-20

申请号：US09417830

申请日：1999-10-12

申请人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Juan-Yuan Wu

发明人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Juan-Yuan Wu

IPC分类号： H01L214763

CPC分类号： H01L21/76834 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31629 ,  H01L21/7681 ,  H01L21/76832

摘要： A method for fabricating dual damascene is to form an undoped silicate glass (USG) liner before forming a fluorinated silicate glass (FSG) layer which serves as an inter-metal dielectric (IMD) layer on a semiconductor substrate. As a result, the surface sensitivity is eliminated, while a FSG layer with a more uniform thickness and a higher reliability is obtained. In addition, the USG liner increases the adhesion between the FSG layer and other material layers, while no particles are easily formed thereon.

摘要翻译： 制造双镶嵌的方法是在形成在半导体衬底上作为金属间电介质（IMD）层的氟化硅酸盐玻璃（FSG）层之前形成未掺杂的硅酸盐玻璃（USG）衬垫。 结果，消除了表面灵敏度，而获得了具有更均匀厚度和更高可靠性的FSG层。 此外，USG衬垫增加了FSG层和其它材料层之间的粘附性，而在其上不容易形成颗粒。

公开(公告)号：US06293850B1

公开(公告)日：2001-09-25

申请号：US09426937

申请日：1999-10-22

申请人： Juen-Kuen Lin ,  Chien-Hsin Lai ,  Peng-Yih Peng ,  Kun-Lin Wu ,  Daniel Chiu ,  Chih-Chiang Yang ,  Juan-Yuan Wu ,  Hao-Kuang Chiu

发明人： Juen-Kuen Lin ,  Chien-Hsin Lai ,  Peng-Yih Peng ,  Kun-Lin Wu ,  Daniel Chiu ,  Chih-Chiang Yang ,  Juan-Yuan Wu ,  Hao-Kuang Chiu

IPC分类号： B24B100

CPC分类号： B24B37/32 ,  B24B37/042 ,  B24B57/02

摘要： A chemical mechanical polishing machine and a fabrication process using the same. The chemical mechanical polishing machine comprises a retainer ring having a plurality of slurry passages at the bottom of the retainer ring. The retainer ring further comprises a circular path. By conducting the slurry through the slurry passages and the circular, a wafer is planarized within the chemical mechanical polishing machine.

公开(公告)号：US06261977B1

公开(公告)日：2001-07-17

申请号：US09391357

申请日：1999-09-08

申请人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Juan-Yuan Wu

发明人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Juan-Yuan Wu

IPC分类号： H01L21324

CPC分类号： H01L21/67069 ,  H01L21/6831 ,  H01L21/6833 ,  Y10S438/905 ,  Y10S438/906 ,  Y10S438/907

摘要： The present invention relates to a method for preventing an electrostatic chuck positioned at the bottom of a plasma vacuum chamber from being corroded during a cleaning process. The electrostatic chuck comprises a conductive substrate functioned as a lower electrode in a plasma process, and an insulating layer on the conductive substrate to electrically isolate the semiconductor wafer and the conductive substrate. The cleaning process involves a plasma process in which a fluorine-contained gas is injected into the plasma vacuum chamber to remove the chemical layer on the inner wall of the plasma vacuum chamber. A ceramic shutter made of SiC material is reposed on the electrostatic chuck and a high DC voltage is applied to the conductive substrate and the ceramic shutter which causes the ceramic shutter and the electrostatic chuck tightly stick together due to an electrostatic reaction. By doing so, the fluorine-contained gas cannot corrode the insulating layer under the ceramic shutter through the gap between the ceramic shutter and the electrostatic chuck.

摘要翻译： 本发明涉及一种防止位于等离子体真空室底部的静电卡盘在清洗过程中被腐蚀的方法。 静电卡盘包括在等离子体工艺中用作下电极的导电基板和导电基板上的绝缘层，以电绝缘半导体晶片和导电基板。 清洗过程涉及等离子体处理，其中将含氟气体注入到等离子体真空室中以除去等离子体真空室的内壁上的化学层。 由SiC材料制成的陶瓷快门被放置在静电卡盘上，并且高导电性基板和陶瓷快门上施加高的直流电压，导致陶瓷快门和静电卡盘由于静电反应紧紧地粘在一起。 通过这样做，含氟气体不能通过陶瓷快门和静电卡盘之间的间隙腐蚀陶瓷快门下面的绝缘层。

公开(公告)号：US06246119B1

公开(公告)日：2001-06-12

申请号：US09432884

申请日：1999-11-02

申请人： Juan-Yuan Wu ,  Water Lur

发明人： Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L23535

CPC分类号： H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene structure includes a semiconductor substrate, a metal-oxide-semiconductor (MOS) transistor formed on the substrate and a metal layer. The metal layer is electrically connected to the conducting regions of the MOS transistor through interconnect. The metal layer further includes first metal spacing regions and second metal spacing regions, wherein the width of a first metal spacing region is about 1 to 10 times of the linewidth of the device, and the width of a second spacing region is about 0.8 to 1.2 times of the linewidth of the device. The first metal spacing regions includes a high-permittivity dielectric for a better thermal transferring rate, and the second spacing regions includes a low-permittivity dielectric for a shorter resistance-capacitance delay.

摘要翻译： 双镶嵌结构包括半导体衬底，形成在衬底上的金属氧化物半导体（MOS）晶体管和金属层。 金属层通过互连电连接到MOS晶体管的导电区域。 金属层还包括第一金属间隔区域和第二金属间隔区域，其中第一金属间隔区域的宽度为器件线宽的约1至10倍，第二间隔区域的宽度为约0.8至1.2 设备线宽的倍数。 第一金属间隔区域包括用于更好的热传递速率的高介电常数电介质，并且第二间隔区域包括用于较短电阻 - 电容延迟的低介电常数介电层。

公开(公告)号：US06239018B1

公开(公告)日：2001-05-29

申请号：US09241326

申请日：1999-02-01

申请人： Chih-Chien Liu ,  Juan-Yuan Wu ,  Water Lur

发明人： Chih-Chien Liu ,  Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L21316

CPC分类号： H01L21/02112 ,  C23C16/50 ,  H01L21/02107 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612

摘要： A method for forming dielectric layers is described. Wiring lines are formed on a provided semiconductor substrate. Spacers are formed on the sidewalls of the wiring lines. A liner layer is formed on the wiring lines and on the spacers by a first HDPCVD step, such as unbiased, unclamped HDPCVD. A dielectric layer is formed on the liner layer to cover the wiring lines and to fill gaps between the wiring lines by a second HDPCVD step.

摘要翻译： 描述形成电介质层的方法。 配线在所提供的半导体衬底上形成。 间隔件形成在布线的侧壁上。 通过第一HDPCVD步骤，例如无偏压，未夹紧的HDPCVD，在布线和间隔物上形成衬垫层。 在衬垫层上形成介电层以覆盖布线，并通过第二HDPCVD步骤填充布线之间的间隙。

公开(公告)号：US06203863B1

公开(公告)日：2001-03-20

申请号：US09200893

申请日：1998-11-27

申请人： Chih-Chien Liu ,  Juan-Yuan Wu ,  Water Lur ,  Shih-Wei Sun

发明人： Chih-Chien Liu ,  Juan-Yuan Wu ,  Water Lur ,  Shih-Wei Sun

IPC分类号： B05D306

CPC分类号： H01L21/02164 ,  C23C16/045 ,  C23C16/50 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76834 ,  H01L21/76837

摘要： A method of gap filling by using HDPCVD. On a substrate having a conductive structure, a first oxide layer is formed to protect the conductive structure. While forming the first oxide layer no bias is applied. An argon flow with a high speed of etching/deposition is provided to form a second oxide layer. While forming the second oxide layer a triangular or trapezium profile is formed due to an etching effect to the corner. An argon flow with a low speed of etching/deposition is provided to form a third oxide layer. The gap filling is completed.

摘要翻译： 使用HDPCVD的间隙填充方法。 在具有导电结构的基板上形成第一氧化物层以保护导电结构。 当形成第一氧化物层时，不施加偏压。 提供具有高速蚀刻/沉积的氩气流以形成第二氧化物层。 在形成第二氧化物层的同时，由于对拐角的蚀刻效果，形成三角形或梯形轮廓。 提供具有低速蚀刻/沉积的氩气流以形成第三氧化物层。 间隙填充完成。

公开(公告)号：US06174793B1

公开(公告)日：2001-01-16

申请号：US09415798

申请日：1999-10-11

申请人： Cheng-Yuan-Chen Tsai ,  Chih-Chien Liu ,  Juan-Yuan Wu

发明人： Cheng-Yuan-Chen Tsai ,  Chih-Chien Liu ,  Juan-Yuan Wu

IPC分类号： H01L213205

CPC分类号： H01L21/76867 ,  H01L21/76838 ,  H01L21/7685 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for enhancing adhesion ability between copper and silicon nitride is disclosed. The present method comprises following steps: first, provide a substrate and then form a copper layer on the substrate; second, form a copper phosphide layer on the copper layer; and finally, form a silicon nitride layer on the copper phosphide layer. Herein, the copper phosphide layer is formed by a plasma enhanced chemical vapor deposition process. Therefore, any copper oxide layer that covers copper layer is replaced by the silicon phosphide layer and then adhesion between copper and silicon nitride is improved. Moreover, the silicon phosphide comprises two advantages: low resistance than copper oxide and efficiently prevent copper diffuses into surrounding dielectric layer.

摘要翻译： 公开了一种提高铜和氮化硅之间粘附能力的方法。 本发明方法包括以下步骤：首先提供衬底，然后在衬底上形成铜层; 第二，在铜层上形成磷化铜层; 最后在磷化铜层上形成氮化硅层。 这里，通过等离子体增强化学气相沉积工艺形成磷化铜层。 因此，覆盖铜层的任何铜氧化物层被磷化硅层代替，然后提高铜和氮化硅之间的粘附。 此外，磷化硅具有两个优点：电阻低于铜氧化物，并有效地防止铜扩散到周围的电介质层。