公开(公告)号：US06252444B1

公开(公告)日：2001-06-26

申请号：US09391373

申请日：1999-09-08

Applicant: Kang-Bok Lee

Inventor： Kang-Bok Lee

IPC: H04L700

CPC classification number: H03L7/07 ,  G06F1/24 ,  H03L7/095

Abstract: A reset signal generation circuit of the present invention includes a phase locked loop (PLL) selector, a plurality of PLLs, a locking detector, a clock selector, a counter, and a reset synchronizer. The PLL selector is activated when an external reset signal is high and provides a signal for selecting one of the plurality of PLLs according to a power down control signal and a PLL selection signal. The plurality of PLLs have different input frequency signals and different output frequency signals. They are activated in response to an external clock signal and inactivated in response to the power down control signal. The locking detector detects locking/unlocking of the PLLs based upon the output frequency signals of the PLLs and generates a locking signal. The clock selector selectively provides one of the output signals of the PLLs and the external clock signal. The counter is coupled to the clock selector and generates an overflow signal after completing count of a predetermined number. In response to the overflow signal of the counter, the reset synchronizer generates an internal reset signal synchronizing with the locking signal. The present invention controls the stable reset mode release time regardless of the settling time of the oscillation signal by controlling the reset signal using the locking signal of the PLL. A current state is maintained even though the locking state of the PLL is released, so the operation of the chip is not influenced by the reset of the PLL.

Abstract translation: 本发明的复位信号生成电路包括锁相环（PLL）选择器，多个PLL，锁定检测器，时钟选择器，计数器和复位同步器。 当外部复位信号为高电平时，PLL选择器被激活，并根据掉电控制信号和PLL选择信号提供用于选择多个PLL之一的信号。 多个PLL具有不同的输入频率信号和不同的输出频率信号。 它们被响应于外部时钟信号而被激活，并且响应于掉电控制信号被去激活。 锁定检测器基于PLL的输出频率信号检测PLL的锁定/解锁，并产生锁定信号。 时钟选择器选择性地提供PLL的输出信号和外部时钟信号之一。 计数器耦合到时钟选择器，并在完成预定数目的计数之后产生溢出信号。 响应于计数器的溢出信号，复位同步器产生与锁定信号同步的内部复位信号。 本发明通过使用PLL的锁定信号控制复位信号来控制振荡信号的稳定时间的稳定的复位模式释放时间。 即使PLL的锁定状态被解除，也保持当前状态，因此芯片的操作不受PLL复位的影响。