METHOD FOR DESIGNING OPTICAL LITHOGRAPHY MASKS FOR DIRECTED SELF-ASSEMBLY
    52.
    发明申请
    METHOD FOR DESIGNING OPTICAL LITHOGRAPHY MASKS FOR DIRECTED SELF-ASSEMBLY 有权
    用于指导自组装的光学绘图掩模的方法

    公开(公告)号:US20110209106A1

    公开(公告)日:2011-08-25

    申请号:US12708570

    申请日:2010-02-19

    IPC分类号: G06F17/50

    摘要: A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate.

    摘要翻译: 一种用于设计光学掩模的方法和计算机系统,用于在基底上的光致抗蚀剂层中形成预模式开口,其中光致抗蚀剂层和预图案开口用自组装材料涂覆,所述自组装材料经过定向自组装以形成定向自身 装配模式 所述方法包括:从目标设计形状生成掩模设计形状; 基于掩模设计形状产生子分辨率辅助特征设计形状; 使用计算机基于子分辨率辅助特征设计形状生成预绘图形状; 并且使用计算机来评估基于预图案形状的自组装材料的定向自组装图案是否在基板上的目标设计形状的尺寸和位置目标的指定范围内。

    Near-Infrared Absorbing Film Compositions
    53.
    发明申请
    Near-Infrared Absorbing Film Compositions 有权
    近红外吸收膜组合物

    公开(公告)号:US20110042653A1

    公开(公告)日:2011-02-24

    申请号:US12543003

    申请日:2009-08-18

    CPC分类号: G03F7/091 G03F9/7026

    摘要: A curable liquid formulation containing at least (i) one or more near-infrared absorbing triphenylamine-based dyes, and (ii) one or more casting solvents. The invention is also directed to solid near-infrared absorbing films composed of crosslinked forms of the curable liquid formulation. The invention is also directed to a microelectronic substrate containing a coating of the solid near-infrared absorbing film as well as a method for patterning a photoresist layer coated on a microelectronic substrate in the case where the near-infrared absorbing film is between the microelectronic substrate and a photoresist film.

    摘要翻译: 包含至少(i)一种或多种近红外吸收性三苯胺类染料的可固化液体制剂,和(ii)一种或多种浇铸溶剂。 本发明还涉及由可固化液体制剂的交联形式组成的固体近红外吸收膜。 本发明还涉及一种含有固体近红外线吸收膜的涂层的微电子衬底,以及在近红外吸收膜位于微电子衬底之间的情况下,用于图案化涂覆在微电子衬底上的光刻胶层的方法 和光刻胶膜。

    Directed self-assembly of block copolymers using segmented prepatterns
    54.
    发明申请
    Directed self-assembly of block copolymers using segmented prepatterns 有权
    使用分段预制图的嵌段共聚物的定向自组装

    公开(公告)号:US20100294740A1

    公开(公告)日:2010-11-25

    申请号:US12468391

    申请日:2009-05-19

    IPC分类号: H01B13/00 B05D7/24 B05D3/00

    摘要: An opening in a substrate is formed, e.g., using optical lithography, with the opening having sidewalls whose cross section is given by segments that are contoured and convex. The cross section of the opening may be given by overlapping circular regions, for example. The sidewalls adjoin at various points, where they define protrusions. A layer of polymer including a block copolymer is applied over the opening and the substrate, and allowed to self-assemble. Discrete, segregated domains form in the opening, which are removed to form holes, which can be transferred into the underlying substrate. The positions of these domains and their corresponding holes are directed to predetermined positions by the sidewalls and their associated protrusions. The distances separating these holes may be greater or less than what they would be if the block copolymer (and any additives) were to self-assemble in the absence of any sidewalls.

    摘要翻译: 例如使用光刻法形成衬底中的开口,其中开口具有侧壁,其横截面由轮廓和凸形的部分给出。 例如,开口的横截面可以由重叠的圆形区域给出。 侧壁在各个点处相邻,在那里它们限定突起。 将包含嵌段共聚物的聚合物层施加在开口和基底上,并允许自组装。 在开口中形成离散的,分离的畴,其被去除以形成孔,其可以转移到下面的基底中。 这些区域及其对应的孔的位置通过侧壁及其相关联的突起被引导到预定位置。 分离这些孔的距离可以大于或小于如果嵌段共聚物(和任何添加剂)在没有任何侧壁的情况下自组装就会发生。

    Microelectronic circuit structure with layered low dielectric constant regions
    55.
    发明授权
    Microelectronic circuit structure with layered low dielectric constant regions 失效
    微电子电路结构具有层状低介电常数区域

    公开(公告)号:US07692308B2

    公开(公告)日:2010-04-06

    申请号:US12256735

    申请日:2008-10-23

    IPC分类号: H01L29/40

    摘要: The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes.

    摘要翻译: 电路结构包括至少两个大致平行的导体结构,以及多个基本上水平的层介质材料层,散布着基本上水平延伸的相对较低的介电常数(低k)体积。 基本水平的层和基本上水平延伸的体积通常介于至少两个大致平行的导体结构之间。 还包括在基本水平的层内密封的多个基本上垂直延伸的相对低k的体积,以及在至少两个大致平行的导体结构之间的基本水平延伸的体积。 与不包括相对低k体积的其他可比较的微电子电路相比,基本垂直延伸的相对低k体积和基本水平延伸的相对低k体积减小了至少两个大致平行的导体结构之间的寄生电容。

    Empty vias for electromigration during electronic-fuse re-programming
    56.
    发明授权
    Empty vias for electromigration during electronic-fuse re-programming 有权
    电子熔丝重新编程期间用于电迁移的空通孔

    公开(公告)号:US07671444B2

    公开(公告)日:2010-03-02

    申请号:US11767580

    申请日:2007-06-25

    摘要: The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device.

    摘要翻译: 本公开总体上涉及集成电路(IC)芯片制造,更具体地,涉及包括开口,层间电介质中的第一通孔和第二通孔的电熔丝装置,其中开口,第一通孔和第二通孔 连接到层间电介质下面的互连; 包围第一通孔和第二通孔的电介质层; 以及在所述介电层上的金属层,其中所述金属层用金属填充所述开口,并且其中所述第一通孔和所述第二通孔基本为空,以允许在所述电熔丝装置的重新编程期间所述互连件的电迁移。

    Sub-lithographic feature patterning using self-aligned self-assembly polymers
    58.
    发明授权
    Sub-lithographic feature patterning using self-aligned self-assembly polymers 有权
    使用自对准自组装聚合物的亚光刻特征图案

    公开(公告)号:US07605081B2

    公开(公告)日:2009-10-20

    申请号:US11424963

    申请日:2006-06-19

    IPC分类号: H01L21/44

    摘要: A method for conducting sub-lithography feature patterning of a device structure is provided. First, a lithographically patterned mask layer that contains one or more mask openings of a diameter d is formed by lithography and etching over an upper surface of the device structure. Next, a layer of a self-assembling block copolymer is applied over the lithographically patterned mask layer and then annealed to form a single unit polymer block of a diameter w inside each of the mask openings, provided that w

    摘要翻译: 提供了一种用于进行子光刻特征图案化的器件结构的方法。 首先,通过在器件结构的上表面上的光刻和蚀刻来形成包含直径d的一个或多个掩模开口的光刻图案掩模层。 接下来,将一层自组装嵌段共聚物施加在光刻图案化的掩模层上,然后退火以在每个掩模开口内形成直径为w的单个单元聚合物嵌段,条件是w

    METHOD AND STRUCTURE FOR RELIEVING TRANSISTOR PERFORMANCE DEGRADATION DUE TO SHALLOW TRENCH ISOLATION INDUCED STRESS
    59.
    发明申请
    METHOD AND STRUCTURE FOR RELIEVING TRANSISTOR PERFORMANCE DEGRADATION DUE TO SHALLOW TRENCH ISOLATION INDUCED STRESS 有权
    用于缓解晶体管分离诱导应力的晶体管性能降解的方法和结构

    公开(公告)号:US20090206442A1

    公开(公告)日:2009-08-20

    申请号:US12033322

    申请日:2008-02-19

    IPC分类号: H01L21/762 H01L23/58

    CPC分类号: H01L21/76232

    摘要: A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate.

    摘要翻译: 一种形成用于半导体器件的浅沟槽隔离(STI)区域的方法,所述方法包括在半导体衬底内限定STI沟槽开口; 用初始沟槽填充材料填充STI沟槽开口; 在对应于STI沟槽开口的位置处限定衬底上的纳米尺度开口的图案; 将纳米级开口的图案转移到沟槽填充材料中,以便在沟槽填充材料中限定多个垂直取向的纳米级开口; 并用另外的沟槽填充材料堵塞纳米级开口的上部,从而在衬底中限定多孔STI区域。

    Method of forming film stack having under layer for preventing pinhole defects
    60.
    发明授权
    Method of forming film stack having under layer for preventing pinhole defects 有权
    形成具有下层以防止针孔缺陷的薄膜叠层的方法

    公开(公告)号:US07541065B2

    公开(公告)日:2009-06-02

    申请号:US11820302

    申请日:2007-06-18

    IPC分类号: B05D7/00

    摘要: A method is provided for forming a film stack in which a first film including a first polymer is formed on a substrate. A second film, which can include a second polymer other than the first polymer, is formed to have an inner surface disposed on the first film. The second film can have a thickness at which a free energy of the second film would be negative if the second film were disposed directly on the substrate. Desirably, the resulting second film is substantially free of dewetting defects.

    摘要翻译: 提供了一种用于形成膜叠层的方法,其中在基板上形成包括第一聚合物的第一膜。 可以包括第一聚合物以外的第二聚合物的第二膜形成为具有设置在第一膜上的内表面。 如果第二膜直接设置在基板上,则第二膜可以具有第二膜的自由能为负的厚度。 理想地,所得到的第二膜基本上没有脱湿缺陷。