Semiconductor Constructions, and Electronic Systems
    54.
    发明申请
    Semiconductor Constructions, and Electronic Systems 有权
    半导体建筑和电子系统

    公开(公告)号:US20090072347A1

    公开(公告)日:2009-03-19

    申请号:US12276235

    申请日:2008-11-21

    CPC classification number: H01L29/7833 H01L21/76205

    Abstract: The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2 being present to a concentration of from about 2% to about 40%, by volume. An oxide structure formed under the bottom corner of a transistor gate stack can have a bottom surface with a topography that includes a step of at least about 50 Å, and an upper surface directly over the bottom surface and having a topography that is substantially planar. Methodology of the present invention can be utilized to form semiconductor constructions suitable for incorporation into highly integrated circuitry. The highly integrated circuitry can be incorporated into electronic systems, and can, for example, be utilized in processors and/or memory storage devices.

    Abstract translation: 本发明包括在晶体管栅极堆叠和相邻沟槽隔离区域的角落处形成氧化物结构的方法。 这样的方法可以包括将半导体材料暴露于蒸汽和H2,其中H2以体积计约2%至约40%的浓度存在。 形成在晶体管栅极堆叠的底角下方的氧化物结构可以具有底表面,其具有包括至少约为50埃的步骤的形貌,以及直接在底表面上方的上表面,并且具有基本平坦的形貌。 本发明的方法可以用于形成适合并入高度集成电路的半导体结构。 高度集成的电路可以并入到电子系统中,并且可以例如在处理器和/或存储器存储设备中使用。

    Semiconductor processing methods
    56.
    发明授权
    Semiconductor processing methods 有权
    半导体加工方法

    公开(公告)号:US07473615B2

    公开(公告)日:2009-01-06

    申请号:US11197882

    申请日:2005-08-05

    CPC classification number: H01L29/7833 H01L21/76205

    Abstract: The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2 being present to a concentration of from about 2% to about 40%, by volume. An oxide structure formed under the bottom corner of a transistor gate stack can have a bottom surface with a topography that includes a step of at least about 50 Å, and an upper surface directly over the bottom surface and having a topography that is substantially planar. Methodology of the present invention can be utilized to form semiconductor constructions suitable for incorporation into highly integrated circuitry. The highly integrated circuitry can be incorporated into electronic systems, and can, for example, be utilized in processors and/or memory storage devices.

    Abstract translation: 本发明包括在晶体管栅极堆叠和相邻沟槽隔离区域的角落处形成氧化物结构的方法。 这样的方法可以包括将半导体材料暴露于蒸汽和H2,其中H2以体积计约2%至约40%的浓度存在。 形成在晶体管栅极堆叠的底角下方的氧化物结构可以具有底表面,其具有包括至少约为50埃的步骤的形貌,以及直接在底表面上方的上表面,并且具有基本平坦的形貌。 本发明的方法可以用于形成适合并入高度集成电路的半导体结构。 高度集成的电路可以并入到电子系统中,并且可以例如在处理器和/或存储器存储设备中使用。

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