公开(公告)号：US20120104512A1

公开(公告)日：2012-05-03

申请号：US12914132

申请日：2010-10-28

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

IPC分类号： H01L27/088 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L29/4991 ,  H01L21/823468 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545

摘要： A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the dielectric layer and the contact.

摘要翻译： 一种包括衬底的半导体芯片; 介电层; 所述电介质层内的栅极，所述栅极包括侧壁; 接触所述门的一部分和所述侧壁的一部分的接触; 以及侧壁，介电层和接触件之间的密封气隙。

公开(公告)号：US07943480B2

公开(公告)日：2011-05-17

申请号：US12029800

申请日：2008-02-12

申请人： Daniel C. Edelstein ,  Nicholas C. M. Fuller ,  David V. Horak ,  Elbert E. Huang ,  Wai-Kin Li ,  Anthony D. Lisi ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Daniel C. Edelstein ,  Nicholas C. M. Fuller ,  David V. Horak ,  Elbert E. Huang ,  Wai-Kin Li ,  Anthony D. Lisi ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/00

CPC分类号： H01L21/7682 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

摘要： Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.

摘要翻译： 公开了亚光刻尺寸气隙形成和相关结构。 在一个实施例中，一种方法包括在衬底上形成包括互连的介质层; 在电介质层上沉积盖层; 在所述盖层上沉积光致抗蚀剂; 图案化光致抗蚀剂以包括最多部分地覆盖互连的第一沟槽图案; 在所述第一沟槽图案内形成间隔物以形成具有亚光刻尺寸的第二沟槽图案; 将所述第二沟槽图案转移到所述覆盖层中并进入所述互连之间的所述介电层; 并且通过夹住介电层中的沟槽而沉积另一介质层以形成气隙。

公开(公告)号：US20090200636A1

公开(公告)日：2009-08-13

申请号：US12029800

申请日：2008-02-12

申请人： Daniel C. Edelstein ,  Nicholas C. M. Fuller ,  David V. Horak ,  Elbert E. Huang ,  Wai-Kin Li ,  Anthony D. Lisi ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Daniel C. Edelstein ,  Nicholas C. M. Fuller ,  David V. Horak ,  Elbert E. Huang ,  Wai-Kin Li ,  Anthony D. Lisi ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/00 ,  H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

摘要： Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.

摘要翻译： 公开了亚光刻尺寸气隙形成和相关结构。 在一个实施例中，一种方法包括在衬底上形成包括互连的介质层; 在电介质层上沉积盖层; 在所述盖层上沉积光致抗蚀剂; 图案化光致抗蚀剂以包括最多部分地覆盖互连的第一沟槽图案; 在所述第一沟槽图案内形成间隔物以形成具有亚光刻尺寸的第二沟槽图案; 将所述第二沟槽图案转移到所述覆盖层中并进入所述互连之间的所述介电层; 并且通过夹住介电层中的沟槽而沉积另一介质层以形成气隙。

公开(公告)号：US08482132B2

公开(公告)日：2013-07-09

申请号：US12575980

申请日：2009-10-08

申请人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

发明人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/82 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/0502 ,  H01L2224/05099 ,  H01L2224/05547 ,  H01L2224/05554 ,  H01L2224/0556 ,  H01L2224/05599 ,  H01L2224/08121 ,  H01L2224/80001 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80359 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/821 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00 ,  H01L2224/80 ,  H01L2224/82

摘要： Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.

公开(公告)号：US20120175775A1

公开(公告)日：2012-07-12

申请号：US13424651

申请日：2012-03-20

申请人： David V. Horak ,  Takeshi Nogami ,  Shom Ponoth ,  Chih-Chao Yang

发明人： David V. Horak ,  Takeshi Nogami ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.

摘要翻译： 包括电迁移屏障的集成电路包括线，该线包括第一导电材料，该线还包括由一个或多个电迁移屏障隔开的多个线段，其中所述一个或多个电迁移屏障包括隔离的第二导电材料 线路各部分的电迁移效应。

公开(公告)号：US07687877B2

公开(公告)日：2010-03-30

申请号：US12115944

申请日：2008-05-06

申请人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

发明人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L23/53295 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure is provided that includes a dielectric material 52′ having a dielectric constant of 4.0 or less and including a plurality of conductive features 56 embedded therein. The dielectric material 52′ has an upper surface 52r that is located beneath an upper surface of each of the plurality of conductive features 56. A first dielectric cap 58 is located on the upper surface of the dielectric material 52′ and extends onto at least a portion of the upper surface of each of the plurality of conductive features 56. As shown, the first dielectric cap 58 forms an interface 59 with each of the plurality of conductive features 56 that is opposite to an electrical field that is generated by neighboring conductive features. The inventive structure also includes a second dielectric cap 60 located on an exposed portion of the upper surface of each of the plurality of conductive features 56 not covered with the first dielectric cap 58. The second dielectric cap 60 further covers on an exposed surface of the first dielectric cap 58.

摘要翻译： 提供一种互连结构，其包括介电常数为4.0或更小的介电材料52'，并且包括嵌入其中的多个导电特征56。 电介质材料52'具有位于多个导电特征56中的每一个的上表面下方的上表面52r。第一电介质盖58位于电介质材料52'的上表面上并延伸至至少一个 多个导电特征56中的每一个的上表面的一部分。如图所示，第一电介质盖58形成接口59，多个导电特征56中的每一个与由相邻导电特征 。 本发明的结构还包括位于多个导电特征56的每一个的上表面的未被第一电介质盖58覆盖的暴露部分上的第二电介质帽60.第二电介质帽60还覆盖在 第一电介质盖58。

公开(公告)号：US20130320411A1

公开(公告)日：2013-12-05

申请号：US13488581

申请日：2012-06-05

申请人： Su-Chen Fan ,  Balasubramanian S. Haran ,  David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Su-Chen Fan ,  Balasubramanian S. Haran ,  David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/66545

摘要： A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region.

公开(公告)号：US08404582B2

公开(公告)日：2013-03-26

申请号：US12773306

申请日：2010-05-04

申请人： David V Horak ,  Takeshi Nogami ,  Shom Ponoth ,  Chih-Chao Yang

发明人： David V Horak ,  Takeshi Nogami ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L23/53238 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level.

摘要翻译： 提供具有自对准电介质盖的互连结构。 在基板上形成至少一个金属化层。 电介质盖被选择性地沉积在金属化层上。

公开(公告)号：US20120153503A1

公开(公告)日：2012-06-21

申请号：US13407933

申请日：2012-02-29

申请人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

IPC分类号： H01L23/522

CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

公开(公告)号：US20110101538A1

公开(公告)日：2011-05-05

申请号：US12610624

申请日：2009-11-02

申请人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

摘要翻译： 本发明的实施例提供了一种创建具有不同长度的通孔和沟槽的方法。 该方法包括在半导体结构的顶部上沉积多个电介质层，多个电介质层被至少一个蚀刻停止层隔开; 通过非选择性蚀刻工艺从所述多个电介质层的顶表面形成多个开口到多个介电层中，其中所述多个开口中的至少一个具有在所述蚀刻步骤层下方的深度; 以及通过选择性蚀刻工艺继续蚀刻多个开口，直到位于蚀刻停止层上方的多个开口的一个或多个开口到达和暴露蚀刻停止层。 还提供了由此制成的半导体结构。