摘要:
An LCD device preventing a short-circuit of adjacent link lines is disclosed. The LCD device includes a pixel area in which a plurality of gate lines and a plurality of data lines crossing the plurality of gate lines at a right angle are formed, a pad area formed at a side of the pixel area, a gate pad portion and a data pad portion formed in the pad area and respectively connected to the plurality of gate lines and the plurality of data lines, first, second, third, and fourth gate link lines connected to the plurality of gate lines and the gate pad portion and alternately arranged with an insulation layer interposed between the first, second, third, and fourth gate link lines, and first and second auto probe pads electrically connected to the first, second, third, and fourth gate link lines. The first and second gate link lines are connected to the first auto probe pad and the third and fourth gate link lines are connected to the second auto probe pad.
摘要:
A display device for managing power supply in an active stand-by mode is disclosed. More specifically, the display device includes a signal mode supply unit which provides control signals for a mode in which a digital cable ready (DCR) feature is selected or for a mode in which a digital video recorder (DVR) feature and a signal processing circuit are selected. Furthermore, the device includes a stand-by power supply unit for supplying power for operating a micro computer and for operating at least one DCR feature if the DCR feature is selected, and a multi-power supply unit for supplying power for operating at least one DVR feature and for operating a signal processing circuit if the DVR feature is selected.
摘要:
A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.
摘要:
This invention provides a process for sequencing nucleic acids using 3′ modified deoxynucleotide analogues or 3′ modified deoxyinosine triphosphate analogues, and 3′ modified dideoxynucleotide analogues having a detectable marker attached thereto.
摘要:
This invention provides a process for sequencing nucleic acids using 3′ modified deoxynucleotide analogs or 3′ modified deoxyinosine triphosphate analogs, and 3′ modified dideoxynucleotide analogs having a detectable marker attached to a base thereof.
摘要:
Provided is a pharmaceutical composition including dead cells of Lactobacillus acidophilus LB strain as an active ingredient for treating or preventing an allergic disease, and may be used to treat and prevent IgE-mediated allergic diseases and non-IgE-mediated allergic diseases such as atopic dermatitis, allergic rhinitis, allergic conjunctivitis, urticaria, and pollinosis by reducing the total content of IgE in the blood.
摘要:
A method for fabricating a universal substrate for attaching biomolecules, including sequencing features and the resulting substrate. A method of direct detection of analytes utilizes a Complementary Metal Oxide Semiconductor (CMOS) sensor with the substrate.
摘要:
A liquid crystal display device adapted to reduce power consumption and to prevent deterioration of the picture quality is disclosed. The liquid crystal display device includes: a substrate; pixel regions defined by a plurality of gate lines and a plurality of data lines arranged on the substrate which are arranged to intersect with each other on the substrate; thin film transistors each formed at intersections of the pluralities of gate and data lines; pixel electrodes formed in each of the pixel regions; a passivation layer formed on an entire surface of the substrate provided with the thin film transistors, the gate lines, the data lines and the pixel electrodes; and common electrode wirings and common electrode patterns formed on the passivation layer, wherein the passivation layer includes a first portions formed on an gate insulation layer opposite to the thin film transistors, gate lines and data lines, and second portions formed on the pixel regions corresponding to the pixel electrodes in a thinner thickness than that of the first portion.