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130 条记录 (耗时 0.039 秒)

    On-chip poly-to-contact process monitoring and reliability evaluation system and method of use
    51.
    发明授权
    On-chip poly-to-contact process monitoring and reliability evaluation system and method of use 有权
    片上多点接触过程监控与可靠性评估系统及使用方法

    公开(公告)号：US09029172B2

    公开(公告)日：2015-05-12

    申请号：US13354547

    申请日：2012-01-20

    申请人： Fen Chen ,  Roger A. Dufresne ,  Timothy D. Sullivan ,  Yanfeng Wang

    发明人： Fen Chen ,  Roger A. Dufresne ,  Timothy D. Sullivan ,  Yanfeng Wang

    IPC分类号： H01L21/00 ,  H01L21/66

    CPC分类号： H01L22/34 ,  H01L22/12 ,  H01L2924/00 ,  H01L2924/0002

    摘要： An on-chip poly-to-contact process monitoring and reliability evaluation system and method of use are provided. A method includes determining a breakdown electrical field of each of one or more shallow trench isolation (STI) measurement structures corresponding to respective one or more original semiconductor structures. The method further includes determining a breakdown voltage of each of one or more substrate measurement structures corresponding to the respective one or more original semiconductor structures. The method further includes determining a space between a gate and a contact of each of the one or more original semiconductor structures based on the determined breakdown electrical field and the determined breakdown voltage.

    摘要翻译： 提供片上多点接触式过程监测和可靠性评估系统及其使用方法。 一种方法包括确定与相应的一个或多个原始半导体结构相对应的一个或多个浅沟槽隔离（STI）测量结构中的每一个的击穿电场。 该方法还包括确定与相应的一个或多个原始半导体结构相对应的一个或多个衬底测量结构中的每一个的击穿电压。 该方法还包括基于所确定的击穿电场和所确定的击穿电压，确定一个或多个原始半导体结构中的每一个的栅极和触点之间的空间。

    Wiring structure and method of forming the structure
    54.
    发明授权
    Wiring structure and method of forming the structure 有权
    布线结构及形成方法

    公开(公告)号：US08569888B2

    公开(公告)日：2013-10-29

    申请号：US13114079

    申请日：2011-05-24

    申请人： Fen Chen ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Timothy D. Sullivan

    发明人： Fen Chen ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Timothy D. Sullivan

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/76816 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.

    摘要翻译： 公开了一种具有导电扩散阻挡层的结构的布线结构和方法，所述导电扩散阻挡层具有较厚的上部和较薄的下部。 较厚的上部位于布线结构和相邻电介质材料之间的接合处。 较厚的上部：（1）最小化金属离子扩散，从而使TDDB; （2）允许在布线结构的顶部实现对于低TDDB最佳的电线宽度与电介质空间宽度比; 和（3）为通孔着陆提供更大的表面积。 较薄的下部：（1）允许在布线结构的其余部分中保持不同的导线宽度与电介质空间宽度比，以平衡其他竞争因素; （2）允许更大的导线截面减小电流密度，从而减少EM; 和（3）避免了布线结构电阻率的增加。

    ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT
    60.
    发明申请
    ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT 有权
    通过电路互连连接

    公开(公告)号：US20120119366A1

    公开(公告)日：2012-05-17

    申请号：US13356013

    申请日：2012-01-23

    申请人： Baozhen Li ,  Paul S. McLaughlin ,  Timothy D. Sullivan

    发明人： Baozhen Li ,  Paul S. McLaughlin ,  Timothy D. Sullivan

    IPC分类号： H01L23/532

    CPC分类号： H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.

    摘要翻译： 在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。 衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。 所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。 或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触 重叠变化。