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    Programmable transceivers that are able to operate over wide frequency ranges
    51.
    发明申请
    Programmable transceivers that are able to operate over wide frequency ranges 有权
    能够在宽频率范围内工作的可编程收发器

    公开(公告)号：US20070127616A1

    公开(公告)日：2007-06-07

    申请号：US11292565

    申请日：2005-12-02

    申请人： Sergey Shumarayev ,  Rakesh Patel

    发明人： Sergey Shumarayev ,  Rakesh Patel

    IPC分类号： H03D3/24

    CPC分类号： H03K19/17744 ,  H03L7/0995

    摘要： A field-programmable gate array (“FPGA”) may include data receiver and/or transmitter circuitry that is adapted to receive and/or transmit data at any frequency(ies) or data rate(s) in a wide range of possible frequencies or data rates. Phase-locked loop (PLL) circuitry may be needed for operation of such receiver and/or transmitter circuitry. For satisfactory operation over the wide frequency range, multiple PLL circuits are provided. One of these PLL circuits may be capable of operating over the entire frequency range, possibly with better jitter performance in some portions of the range than in other portions of the range. One or more other PLL circuits may be provided that are focused on particular parts of the broad range, especially where the jitter performance of the first-mentioned PLL may not be adequate to meet some possible needs.

    摘要翻译： 现场可编程门阵列（“FPGA”）可以包括数据接收器和/或发射机电路，其适于在宽范围的可能频率中以任何频率或数据速率接收和/或发射数据，或 数据速率。 可能需要锁相环（PLL）电路来操作这种接收器和/或发射器电路。 为了在宽频率范围内的令人满意的操作，提供了多个PLL电路。 这些PLL电路中的一个可能能够在整个频率范围内运行，可能在该范围的某些部分中具有比该范围的其他部分更好的抖动性能。 可以提供一个或多个其他PLL电路，其集中在宽范围的特定部分上，特别是在首先提到的PLL的抖动性能可能不足以满足一些可能需要的地方。

    High-speed data reception circuitry and methods
    53.
    发明申请
    High-speed data reception circuitry and methods 有权
    高速数据接收电路和方法

    公开(公告)号：US20070025436A1

    公开(公告)日：2007-02-01

    申请号：US11192539

    申请日：2005-07-28

    申请人： Sergey Shumarayev ,  Wilson Wong ,  Rakesh Patel

    发明人： Sergey Shumarayev ,  Wilson Wong ,  Rakesh Patel

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03573

    摘要： Equalization circuitry for receiving a digital data signal includes both feed-forward equalizer (“FFE”) circuitry and decision-feedback equalizer (“DFE”) circuitry. The FFE circuitry may be used to give the DFE circuitry a signal that is at least minimally adequate for proper start-up of the DFE circuitry. Thereafter, more of the burden of the equalization task may be shifted from the FFE circuitry to the DFE circuitry.

    摘要翻译： 用于接收数字数据信号的均衡电路包括前馈均衡器（“FFE”）电路和判决反馈均衡器（“DFE”）电路。 FFE电路可以用于给DFE电路提供至少最不足以适当启动DFE电路的信号。 此后，均衡任务的更多负担可能从FFE电路转移到DFE电路。

    Programmable slew rate control for differential output
    54.
    发明授权
    Programmable slew rate control for differential output 有权
    差分输出的可编程压摆率控制

    公开(公告)号：US07132847B1

    公开(公告)日：2006-11-07

    申请号：US10708303

    申请日：2004-02-24

    申请人： Wilson Wong ,  Sergey Shumarayev ,  Rakesh Patel

    发明人： Wilson Wong ,  Sergey Shumarayev ,  Rakesh Patel

    IPC分类号： H03K19/003

    CPC分类号： H03K17/6872 ,  H03K17/164

    摘要： A programmable technique is used to control the slew rate of a differential output buffer. A method controls the slew rate (SR) by changing an “on” resistance of the switches used to steer the current. This can be accomplished by (i) using different size switches or (ii) changing the slew rate of the predrivers which drive the final switches. The latter approach has the advantage that it only temporarily increases the “on” resistance, which does not cause any headroom problems after the transient. A specific application is for the differential outputs of a programmable logic integrated circuits.

    摘要翻译： 可编程技术用于控制差分输出缓冲器的转换速率。 一种方法通过改变用于转向电流的开关的“导通”电阻来控制转换速率（SR）。 这可以通过（i）使用不同尺寸的开关或（ii）改变驱动最终开关的预驱动器的转换速率来实现。 后一种方法的优点在于它仅暂时增加了“接通”电阻，这在瞬时之后不会引起任何余量问题。 具体应用是可编程逻辑集成电路的差分输出。

    Administering a communication network
    55.
    发明申请
    Administering a communication network 有权
    管理通信网络

    公开(公告)号：US20060020694A1

    公开(公告)日：2006-01-26

    申请号：US11183156

    申请日：2005-07-14

    申请人： Siddhartha Nag ,  Alfred D'Souza ,  Neveed Alam ,  Rakesh Patel

    发明人： Siddhartha Nag ,  Alfred D'Souza ,  Neveed Alam ,  Rakesh Patel

    IPC分类号： G06F3/00

    CPC分类号： H04L41/147 ,  H04L29/06027 ,  H04L41/0213 ,  H04L41/0806 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/145 ,  H04L41/20 ,  H04L41/22 ,  H04L65/1009 ,  H04L65/1069 ,  H04L65/80 ,  H04M7/0081

    摘要： Methods and apparatus are provided for administering a communication network. In one embodiment, a first interface screen depicts nodes within a network. The nodes include a pair of media aggregation managers providing multiplexing/demultiplexing of media traffic associated with multiple application sessions between a pair of communities onto a preallocated reservation protocol session between the media aggregation managers. The media aggregation managers are visually distinguishable from other nodes. A second interface screen depicts potential paths through the network. Each potential path is capable of transferring media packets between the media aggregation managers. Via the second user interface screen, a network administrator is capable of initiating (1) path-level configuration of routers that are part of a selected potential path to cause the routers to route media packets exchanged between the pair of communities over the selected path, and (2) establishment of the preallocated reservation protocol session between the media aggregation managers.

    摘要翻译： 提供了用于管理通信网络的方法和装置。 在一个实施例中，第一接口屏幕描绘网络内的节点。 节点包括一对媒体聚合管理器，其将与一对社区之间的多个应用会话相关联的媒体流量复用/解复用到媒体聚合管理器之间的预先分配的预留协议会话。 媒体聚合管理器在视觉上与其他节点区分开。 第二个界面屏幕描绘了通过网络的潜在路径。 每个潜在路径都能够在媒体聚合管理器之间传送媒体数据包。 通过第二用户界面屏幕，网络管理员能够启动（1）作为所选潜在路径的一部分的路由器的路径级配置，以使路由器路由在所选路径上的一对社区之间交换的媒体分组， 和（2）在媒体聚合管理器之间建立预先分配的预留协议会话。

    Byte alignment for serial data receiver
    56.
    发明授权
    Byte alignment for serial data receiver 失效
    串行数据接收器的字节对齐

    公开(公告)号：US06970117B1

    公开(公告)日：2005-11-29

    申请号：US10789406

    申请日：2004-02-26

    申请人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

    发明人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

    IPC分类号： H03M9/00 ,  H04L7/02

    CPC分类号： H04L7/0054 ,  H03M9/00

    摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

    摘要翻译： 用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。 字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。 内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。 如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。 信号可以指示位滑动电路将边界调整校正对准所需的位数。 或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

    Embedded memory blocks for programmable logic
    57.
    发明授权
    Embedded memory blocks for programmable logic 有权

    公开(公告)号：US06593772B2

    公开(公告)日：2003-07-15

    申请号：US10177785

    申请日：2002-06-19

    申请人： Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang ,  Rakesh Patel ,  Tin Lai

    发明人： Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang ,  Rakesh Patel ,  Tin Lai

    IPC分类号： H03K19177

    CPC分类号： G11C5/025 ,  H03K19/17736 ,  H03K19/1776

    摘要： A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.