Invalidating translation lookaside buffer entries in a virtual machine (VM) system
    52.
    发明申请
    Invalidating translation lookaside buffer entries in a virtual machine (VM) system 有权
    使虚拟机(VM)系统中的翻译后备缓冲区条目无效

    公开(公告)号:US20050080937A1

    公开(公告)日:2005-04-14

    申请号:US10973678

    申请日:2004-10-25

    IPC分类号: G06F12/10 G06F3/00

    摘要: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.

    摘要翻译: 本发明的一个实施例是使翻译后备缓冲器(TLB)中的条目无效的技术。 处理器中的TLB具有多个TLB条目。 当执行无效操作时,每个TLB条目与虚拟机扩展(VMX)标签字相关联,指示相关联的TLB条目是否根据处理器模式而无效。 处理器模式是虚拟机(VM)中的执行之一,而不是虚拟机中的执行。 无效操作属于一个无效的无效操作集合,它由(1)可能为空的操作集合组合,使一组可变数量的TLB条目无效,(2)一组可能的空白操作,使一个TLB无效 条目,(3)使多个TLB条目无效的可能的一组操作,(4)启用和禁用虚拟存储器的使用的可能的一组可能的空操作,以及(5)配置物理的可能的一组操作 地址大小,页面大小或其他虚拟内存系统行为,以改变物理机器解释TLB条目的方式。

    Invalidating translation lookaside buffer entries in a virtual machine (VM) system
    53.
    发明授权
    Invalidating translation lookaside buffer entries in a virtual machine (VM) system 有权
    使虚拟机(VM)系统中的翻译后备缓冲区条目无效

    公开(公告)号:US08543772B2

    公开(公告)日:2013-09-24

    申请号:US12959109

    申请日:2010-12-02

    IPC分类号: G06F12/08

    摘要: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.

    摘要翻译: 本发明的一个实施例是使翻译后备缓冲器(TLB)中的条目无效的技术。 处理器中的TLB具有多个TLB条目。 当执行无效操作时,每个TLB条目与虚拟机扩展(VMX)标签字相关联,指示相关联的TLB条目是否根据处理器模式而无效。 处理器模式是虚拟机(VM)中的执行之一,而不是虚拟机中的执行。 无效操作属于一个无效的无效操作集合,它由(1)可能为空的操作集合组合,使一组可变数量的TLB条目无效,(2)一组可能的空白操作,使一个TLB无效 条目,(3)使多个TLB条目无效的可能的一组操作,(4)启用和禁用虚拟存储器的使用的可能的一组可能的空操作,以及(5)配置物理的可能的一组操作 地址大小,页面大小或其他虚拟内存系统行为,以改变物理机器解释TLB条目的方式。