公开(公告)号：US20060252281A1

公开(公告)日：2006-11-09

申请号：US11366453

申请日：2006-03-03

申请人： Ki-Yeon Park ,  Kyoung-Ryul Yoon ,  Dae-Sik Choi ,  Han-Mei Choi ,  Seung-Hwan Lee

发明人： Ki-Yeon Park ,  Kyoung-Ryul Yoon ,  Dae-Sik Choi ,  Han-Mei Choi ,  Seung-Hwan Lee

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/022 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02247 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/318 ,  H01L29/513 ,  H01L29/7881

摘要： A semiconductor device and/or gate structure having a composite dielectric layer and methods of manufacturing the same is provided. In the semiconductor device, gate structure, and methods provided, a first conductive layer may be formed on a substrate. A native oxide layer formed on the first conductive layer may be removed. A surface of the first conductive layer may be nitrided so that the surface may be altered into a nitride layer. A composite dielectric layer including the first and/or second dielectric layers may be formed on the nitride layer. A second conductive layer may be formed on the composite dielectric layer. The first dielectric layer may include a material having a higher dielectric constant. The second dielectric layer may be capable of suppressing crystallization of the first dielectric layer.

公开(公告)号：US08735247B2

公开(公告)日：2014-05-27

申请号：US13204349

申请日：2011-08-05

申请人： Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Jin-Gyun Kim

发明人： Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Jin-Gyun Kim

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L29/76

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A method for fabricating a nonvolatile memory device is disclosed. The method includes forming a first structure for a common source line on a semiconductor substrate, the first structure extending along a first direction, forming a mold structure by alternately stacking a plurality of sacrificial layers and a plurality of insulating layers on the semiconductor substrate, forming a plurality of openings in the mold structure exposing a portion of the first structure, and forming a first memory cell string at a first side of the first structure and a second memory cell string at a second, opposite side of the first structure. The plurality of openings include a first through-hole and a second through-hole, each through-hole passing through the plurality of sacrificial layers and plurality of insulating layers, and the first through-hole and the second through-hole overlap each other in the first direction.

摘要翻译： 公开了一种用于制造非易失性存储器件的方法。 该方法包括在半导体衬底上形成用于公共源极线的第一结构，第一结构沿着第一方向延伸，通过在半导体衬底上交替堆叠多个牺牲层和多个绝缘层来形成模具结构，形成 所述模具结构中的多个开口露出所述第一结构的一部分，以及在所述第一结构的第一侧形成第一存储单元串，以及在所述第一结构的第二相反侧形成第二存储单元串。 多个开口包括第一通孔和第二通孔，每个通孔穿过多个牺牲层和多个绝缘层，并且第一通孔和第二通孔重叠在一起 第一个方向。

公开(公告)号：US08642458B2

公开(公告)日：2014-02-04

申请号：US13414085

申请日：2012-03-07

申请人： Byung-Hong Chung ,  Young-Hee Kim ,  In-Sun Yi ,  Han-Mei Choi

发明人： Byung-Hong Chung ,  Young-Hee Kim ,  In-Sun Yi ,  Han-Mei Choi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76883 ,  H01L21/28273 ,  H01L21/32115 ,  H01L21/76882 ,  H01L27/11521 ,  H01L29/66825

摘要： A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.

摘要翻译： 一种制造非易失性存储器件的方法包括提供一种中间结构，其中在半导体衬底上相邻设置浮置栅极和隔离膜，并且栅极绝缘膜设置在浮置栅极和隔离膜上，形成 导电膜，并且使导电膜退火，使得浮栅的上部的导电膜的一部分向下流到浮栅的下部和隔离膜的上部。

公开(公告)号：US08426304B2

公开(公告)日：2013-04-23

申请号：US13241316

申请日：2011-09-23

申请人： Dong-Chul Yoo ,  Chan-Jin Park ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Joon-Suk Lee

发明人： Dong-Chul Yoo ,  Chan-Jin Park ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Joon-Suk Lee

IPC分类号： H01L21/4763

CPC分类号： H01L27/11582 ,  H01L27/105 ,  H01L27/11573 ,  H01L27/11575

摘要： Methods of manufacturing a semiconductor device include forming a stopping layer pattern in a first region of a substrate. A first mold structure is formed in a second region of the substrate that is adjacent the first region. The first mold structure includes first sacrificial patterns and first interlayer patterns stacked alternately. A second mold structure is formed on the first mold structure and the stopping layer pattern. The second mold structure includes second sacrificial patterns and second interlayer patterns stacked alternately. The second mold structure partially covers the stopping layer pattern. A channel pattern is formed and passes through the first mold structure and the second mold structure.

摘要翻译： 制造半导体器件的方法包括在衬底的第一区域中形成停止层图案。 第一模具结构形成在与第一区域相邻的基板的第二区域中。 第一模具结构包括交替堆叠的第一牺牲图案和第一层间图案。 在第一模具结构和止挡层图案上形成第二模具结构。 第二模具结构包括交替堆叠的第二牺牲图案和第二层间图案。 第二模具结构部分地覆盖止挡层图案。 形成通道图案并通过第一模具结构和第二模具结构。

公开(公告)号：US08410542B2

公开(公告)日：2013-04-02

申请号：US12938006

申请日：2010-11-02

申请人： Dong-Chul Yoo ,  Byong-Ju Kim ,  Han-Mei Choi ,  Ki-Hyun Hwang

发明人： Dong-Chul Yoo ,  Byong-Ju Kim ,  Han-Mei Choi ,  Ki-Hyun Hwang

IPC分类号： H01L29/792

CPC分类号： H01L29/42324 ,  G11C16/0416 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

摘要： Nonvolatile memory devices include a tunnel insulating layer on a substrate and a charge storing layer on the tunnel insulating layer. A charge transfer blocking layer is provided on the charge storing layer. The charge transfer blocking layer is formed as a composite of multiple layers, which include a first oxide layer having a thickness of about 1 Å to about 10 Å. This first oxide layer is formed directly on the charge storing layer. The charge transfer blocking layer includes a first dielectric layer on the first oxide layer. The charge transfer blocking layer also includes a second oxide layer on the first dielectric layer and a second dielectric layer on the second oxide layer. The first and second dielectric layers have a higher dielectric constant relative to the first and second oxide layers, respectively. The memory cell includes an electrically conductive electrode on the charge transfer blocking layer.

摘要翻译： 非易失性存储器件包括衬底上的隧道绝缘层和隧道绝缘层上的电荷存储层。 电荷转移阻挡层设置在电荷存储层上。 电荷转移阻挡层形成为多层的复合物，其包括厚度为约至约的第一氧化物层。 该第一氧化物层直接形成在电荷存储层上。 电荷转移阻挡层包括在第一氧化物层上的第一电介质层。 电荷转移阻挡层还包括在第一介电层上的第二氧化物层和第二氧化物层上的第二介电层。 第一和第二电介质层分别相对于第一和第二氧化物层具有更高的介电常数。 存储单元包括电荷转移阻挡层上的导电电极。

公开(公告)号：US20120052673A1

公开(公告)日：2012-03-01

申请号：US13204349

申请日：2011-08-05

申请人： Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Jin-Gyun Kim

发明人： Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Jin-Gyun Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A method for fabricating a nonvolatile memory device is disclosed. The method includes forming a first structure for a common source line on a semiconductor substrate, the first structure extending along a first direction, forming a mold structure by alternately stacking a plurality of sacrificial layers and a plurality of insulating layers on the semiconductor substrate, forming a plurality of openings in the mold structure exposing a portion of the first structure, and forming a first memory cell string at a first side of the first structure and a second memory cell string at a second, opposite side of the first structure. The plurality of openings include a first through-hole and a second through-hole, each through-hole passing through the plurality of sacrificial layers and plurality of insulating layers, and the first through-hole and the second through-hole overlap each other in the first direction.

摘要翻译： 公开了一种用于制造非易失性存储器件的方法。 该方法包括在半导体衬底上形成用于公共源极线的第一结构，第一结构沿着第一方向延伸，通过在半导体衬底上交替堆叠多个牺牲层和多个绝缘层来形成模具结构，形成 所述模具结构中的多个开口露出所述第一结构的一部分，以及在所述第一结构的第一侧形成第一存储单元串，以及在所述第一结构的第二相反侧形成第二存储单元串。 多个开口包括第一通孔和第二通孔，每个通孔穿过多个牺牲层和多个绝缘层，并且第一通孔和第二通孔重叠在一起 第一个方向。

公开(公告)号：US08114735B2

公开(公告)日：2012-02-14

申请号：US11902209

申请日：2007-09-20

申请人： Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Seung-Jae Baik ,  Sun-Jung Kim ,  Kwang-Min Park ,  In-Sun Yi

发明人： Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Seung-Jae Baik ,  Sun-Jung Kim ,  Kwang-Min Park ,  In-Sun Yi

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28282 ,  H01L21/3185 ,  H01L29/4234 ,  H01L29/518 ,  H01L29/7923

摘要： In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.

摘要翻译： 在制造非易失性存储器件的方法中，隧道绝缘层可以形成在衬底的沟道区上。 可以在隧道绝缘层上形成包括氮化硅的电荷俘获层，以从沟道区捕获电子。 可以使用包括氮气的第一气体和包括氧的第二气体来进行热处理，以去除电荷捕获层中的缺陷位点并致密化电荷捕获层。 可以在热处理的电荷俘获层上形成阻挡层，然后可以在阻挡层上形成导电层。 阻挡层，导电层，热处理电荷捕获层和隧道绝缘层可以被图案化以在沟道区上形成栅极结构。 因此，可以提高包括门结构的非易失性存储器件的数据保持性能和/或可靠性。

公开(公告)号：US08039054B2

公开(公告)日：2011-10-18

申请号：US10854942

申请日：2004-05-27

申请人： In-Sung Park ,  Young-Wook Park ,  Myeong-Jin Kim ,  Eun-Taek Yim ,  Han-Mei Choi ,  Kyoung-Seok Kim ,  Beung-Keun Lee

发明人： In-Sung Park ,  Young-Wook Park ,  Myeong-Jin Kim ,  Eun-Taek Yim ,  Han-Mei Choi ,  Kyoung-Seok Kim ,  Beung-Keun Lee

IPC分类号： C23C16/00

CPC分类号： C23C16/45531 ,  C23C16/403 ,  C23C16/45527 ,  C23C16/45561

摘要： A layer deposition method includes: feeding a reactant with a first flow of an inert gas as a carrier gas into a reaction chamber to chemisorb the reactant on a substrate; feeding the first flow of the inert gas to purge the reaction chamber and a first reactant feed line; and feeding the second flow of the inert gas into the reaction chamber through a feed line different from the first reactant feed line.

摘要翻译： 层沉积方法包括：将具有作为载气的惰性气体的第一流的反应物进料到反应室中以化学吸附基材上的反应物; 供给惰性气体的第一流以吹扫反应室和第一反应物进料管线; 以及通过不同于第一反应物进料管线的进料管线将惰性气体的第二流量进料到反应室中。

公开(公告)号：US20110101438A1

公开(公告)日：2011-05-05

申请号：US12938006

申请日：2010-11-02

申请人： Dong-Chul Yoo ,  Byong-Ju Kim ,  Han-Mei Choi ,  Ki-Hyun Hwang

发明人： Dong-Chul Yoo ,  Byong-Ju Kim ,  Han-Mei Choi ,  Ki-Hyun Hwang

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L29/42324 ,  G11C16/0416 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

摘要： Nonvolatile memory devices include a tunnel insulating layer on a substrate and a charge storing layer on the tunnel insulating layer. A charge transfer blocking layer is provided on the charge storing layer. The charge transfer blocking layer is formed as a composite of multiple layers, which include a first oxide layer having a thickness of about 1 Å to about 10 Å. This first oxide layer is formed directly on the charge storing layer. The charge transfer blocking layer includes a first dielectric layer on the first oxide layer. The charge transfer blocking layer also includes a second oxide layer on the first dielectric layer and a second dielectric layer on the second oxide layer. The first and second dielectric layers have a higher dielectric constant relative to the first and second oxide layers, respectively. The memory cell includes an electrically conductive electrode on the charge transfer blocking layer.

摘要翻译： 非易失性存储器件包括衬底上的隧道绝缘层和隧道绝缘层上的电荷存储层。 电荷转移阻挡层设置在电荷存储层上。 电荷转移阻挡层形成为多层的复合物，其包括厚度为约至约的第一氧化物层。 该第一氧化物层直接形成在电荷存储层上。 电荷转移阻挡层包括在第一氧化物层上的第一电介质层。 电荷转移阻挡层还包括在第一介电层上的第二氧化物层和第二氧化物层上的第二介电层。 第一和第二电介质层分别相对于第一和第二氧化物层具有更高的介电常数。 存储单元包括电荷转移阻挡层上的导电电极。

公开(公告)号：US07635633B2

公开(公告)日：2009-12-22

申请号：US11898039

申请日：2007-09-07

申请人： Se-Hoon Oh ,  Young-Geun Park ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Ki-Yeon Park ,  Sun-Jung Kim

发明人： Se-Hoon Oh ,  Young-Geun Park ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Ki-Yeon Park ,  Sun-Jung Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

摘要： In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.

摘要翻译： 在非易失性存储器件和制造非易失性存储器件的方法中，隧道绝缘层，电荷俘获层，电介质层和导电层可以顺序形成在衬底的沟道区上。 可以将导电层图案化以形成栅电极，并且可以在栅电极的侧壁上形成间隔物。 可以通过使用间隔物作为蚀刻掩模的各向异性蚀刻工艺在沟道区上形成电介质层图案，电荷俘获层图案和隧道绝缘层图案。 可以通过各向同性蚀刻工艺去除电荷俘获层图案的侧壁以减小其宽度。 因此，电荷捕获层图案中电子的横向扩散的可能性可能会降低或被抑制，并且可以提高非易失性存储器件的高温应力特性。