Three-dimensional position and orientation sensing system
    51.
    发明授权
    Three-dimensional position and orientation sensing system 失效
    三维位置和方向感知系统

    公开(公告)号:US06724930B1

    公开(公告)日:2004-04-20

    申请号:US09498963

    申请日:2000-02-04

    IPC分类号: G06K900

    摘要: A three-dimensional position and orientation sensing apparatus including: an image input section which inputs an image acquired by an image acquisition apparatus and showing at least three markers having color or geometric characteristics as one image, three-dimensional positional information of the markers with respect to an object to be measured being known in advance; a region extracting section which extracts a region corresponding to each marker in the image; a marker identifying section which identifies the individual markers based on the color or geometric characteristics of the markers in the extracted regions; and a position and orientation calculating section which calculates the three-dimensional position and orientation of the object to be measured with respect to the image acquisition apparatus, by using positions of the identified markers in the image input to the image input section, and the positional information of the markers with respect to the object to be measured.

    摘要翻译: 一种三维位置和方向检测装置,包括:图像输入部,其输入由图像获取装置获取的图像,并且将至少三个具有颜色或几何特征的标记显示为一个图像,所述标记的三维位置信息相对于 预先知道要被测量的物体; 区域提取部,其提取与图像中的每个标记对应的区域; 基于提取区域中的标记的颜色或几何特征来识别各个标记的标记识别部分; 以及位置和姿势计算部分,通过使用输入到图像输入部分的图像中识别的标记的位置来计算相对于图像获取装置的待测量对象的三维位置和取向,以及位置 关于待测量对象的标记的信息。

    Intermittent reception control apparatus
    53.
    发明授权
    Intermittent reception control apparatus 失效
    间歇式接收控制装置

    公开(公告)号:US5815819A

    公开(公告)日:1998-09-29

    申请号:US672552

    申请日:1996-06-28

    CPC分类号: H04W52/029 Y02B60/50

    摘要: An intermittent reception waiting time period is roughly counted by counting low frequency clocks using a low frequency clock counter and a remainder of the intermittent reception waiting time period which cannot be counted with a time resolution of the low frequency clocks is counted by counting high frequency clock pulses using a high frequency clock counter with a high time resolution. Outputs of the high frequency clocks are prohibited while the intermittent reception waiting time period is counted by the low frequency clock counter. As a result, accurate start timing of an intermittent reception can be set with reduced power consumption caused by prohibiting the outputs of the high frequency clock pulses.

    摘要翻译: 通过使用低频时钟计数器对低频时钟进行计数,并且通过计数高频时钟来计数不能用低频时钟的时间分辨率计数的间歇接收等待时间段的剩余部分来大致计数间歇接收等待时间段 使用高时钟分辨率的高频时钟计数器。 在通过低频时钟计数器对间歇接收等待时间段进行计数的同时禁止高频时钟的输出。 结果,可以通过禁止高频时钟脉冲的输出而导致的功耗降低来设定间歇接收的准确的开始定时。

    Digital modulator and baseband signal generator for digital modulator
    54.
    发明授权
    Digital modulator and baseband signal generator for digital modulator 失效
    用于数字调制器的数字调制器和基带信号发生器

    公开(公告)号:US5175514A

    公开(公告)日:1992-12-29

    申请号:US825938

    申请日:1992-01-27

    IPC分类号: H04L27/20

    CPC分类号: H04L27/2092

    摘要: A digital modulator includes a signal source for a digital baseband signal and a signal source for carrier phase information. The digital baseband signal is converted into amplitude information of an I phase, a Q phase, an I' phase and a Q' phase by a mapping circuit. The carrier phase information is converted into four phase information with phases shifted by shift registers to be out of phase by .pi./4 from each other. The digital modulator includes four ROM, each ROM outputting a multiplication result of the corresponding amplitude information and carrier signal based on the corresponding one of the four amplitude information as a higher order address and the corresponding one of the four phase information as a lower order address. These outputs are added to each other in a digital manner and then converted into an analog signal which is supplied as a modulated signal.

    摘要翻译: 数字调制器包括用于数字基带信号的信号源和用于载波相位信息的信号源。 数字基带信号通过映射电路被转换为I相,Q相,I'相和Q'相的振幅信息。 载波相位信息被转换成四个相位信息,其相移由移位寄存器彼此异相π/ 4。 数字调制器包括四个ROM,每个ROM基于四个幅度信息中的相应一个作为高阶地址输出对应的幅度信息和载波信号的相乘结果,四个相位信息中的对应一个作为低位地址 。 这些输出以数字方式相互相加,然后被转换成作为调制信号提供的模拟信号。

    Synchronization recovery circuit for recovering word synchronization
    55.
    发明授权
    Synchronization recovery circuit for recovering word synchronization 失效
    用于恢复字同步的同步恢复电路

    公开(公告)号:US5040195A

    公开(公告)日:1991-08-13

    申请号:US452668

    申请日:1989-12-19

    IPC分类号: H04L7/04

    CPC分类号: H04L7/042 H04L7/046

    摘要: In a cellular-type communication system, a receiving apparatus of a mobile station which has received a forward control channel message recovers word synchronization of the received data. More particularly, the receiving apparatus converts serial FOCC data into a 8-bit parallel data signal while generating 8-bit parallel synchronization data indicative of a word synchronizing position in the parallel data above, and thus applies these two parallel data to a microcomputer. The microcomputer detects the synchronizing position of the synchronization data and then determines effectiveness of those data among the data signal that follow the corresponding bit position, for storing them in a memory.