Method and System for MIMO Channel Information Feedback
    51.
    发明申请
    Method and System for MIMO Channel Information Feedback 有权
    MIMO信道反馈的方法和系统

    公开(公告)号:US20120300868A1

    公开(公告)日:2012-11-29

    申请号:US13577789

    申请日:2010-10-22

    IPC分类号: H04B7/06

    摘要: The present invention discloses a method for Multiple Input Multiple Output (MIMO) channel information feedback, and the method includes: a terminal selecting part of column vectors for MIMO system feedback from a codebook matrix W corresponding to a Precoding Matrix Indicator (PMI) and marking the selected part of column vectors as Wpart; the terminal determining information O which represents high-precision vector quantification information of MIMO along with the part of column vectors Wpart according to a common representation relationship F, and feeding back the information O to a base station. The present invention also discloses a terminal and a base station which support MIMO. The present invention achieves high-precision and low-overhead channel information feedback and can well support multiple vector feedback needed by high rank (more layer multiplexing) MIMO transmission and high-precision feedback needed by low rank MIMO transmission simultaneously.

    摘要翻译: 本发明公开了一种多输入多输出(MIMO)信道信息反馈的方法,该方法包括:从对应于预编码矩阵指示符(PMI)的码本矩阵W中选择一部分用于MIMO系统反馈的列向量, 所选的部分列向量为Wpart; 终端确定信息O,其表示MIMO的高精度矢量量化信息以及根据公共表示关系F的列向量Wpart的一部分,并将信息O反馈到基站。 本发明还公开了一种支持MIMO的终端和基站。 本发明实现了高精度和低开销的信道信息反馈,并且可以很好地支持高秩(多层复用)MIMO传输和低秩MIMO传输所需的高精度反馈所需的多向量反馈。

    SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
    52.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 有权
    半导体结构及其形成方法

    公开(公告)号:US20120292711A1

    公开(公告)日:2012-11-22

    申请号:US13202411

    申请日:2011-08-02

    IPC分类号: H01L27/092 H01L21/336

    摘要: A semiconductor structure is provided. The semiconductor structure comprises: a substrate; a gate dielectric layer formed on the substrate; a metal gate electrode layer formed on the gate dielectric layer; and at least one metal-containing adjusting layer for adjusting a work function of the semiconductor structure, in which an interfacial layer is formed between the substrate and the gate dielectric layer, and an energy of bond between a metal atom in the metal-containing adjusting layer and an oxygen atom is larger than that between an atom of materials forming the gate dielectric layer or the interfacial layer and an oxygen atom. Further, a method for forming the semiconductor structure is also provided.

    摘要翻译: 提供半导体结构。 半导体结构包括:基板; 形成在所述基板上的栅介质层; 形成在栅介质层上的金属栅电极层; 以及至少一个用于调节半导体结构的功函数的含金属的调节层,其中在所述基底和所述栅极电介质层之间形成界面层,并且所述含金属调节中的金属原子之间的键能 层和氧原子大于形成栅极介电层或界面层的材料的原子和氧原子之间的氧原子。 此外,还提供了一种用于形成半导体结构的方法。

    COMPLEMENTARY TUNNELING FIELD EFFECT TRANSISTOR AND METHOD FOR FORMING THE SAME
    54.
    发明申请
    COMPLEMENTARY TUNNELING FIELD EFFECT TRANSISTOR AND METHOD FOR FORMING THE SAME 有权
    补充隧道场效应晶体管及其形成方法

    公开(公告)号:US20120267609A1

    公开(公告)日:2012-10-25

    申请号:US13386581

    申请日:2011-11-28

    IPC分类号: H01L27/092 H01L21/8238

    摘要: A complementary tunneling field effect transistor and a method for forming the same are provided. The complementary tunneling field effect transistor comprises: a substrate; an insulating layer, formed on the substrate; a first semiconductor layer, formed on the insulating layer and comprising first and second doped regions; a first type TFET vertical structure formed on a first part of the first doped region and a second type TFET vertical structure formed on a first part of the second doped region, in which a second part of the first doped region is connected with a second part of the second doped region and a connecting portion between the second part of the first doped region and the second part of the second doped region is used as a drain output; and a U-shaped gate structure, formed between the first type TFET vertical structure and the second type TFET vertical structure.

    摘要翻译: 提供互补隧道场效应晶体管及其形成方法。 互补隧道场效应晶体管包括:衬底; 形成在基板上的绝缘层; 第一半导体层,形成在所述绝缘层上并且包括第一和第二掺杂区域; 形成在第一掺杂区域的第一部分上的第一类型TFET垂直结构和形成在第二掺杂区域的第一部分上的第二类型TFET垂直结构,其中第一掺杂区域的第二部分与第二部分 的第二掺杂区域的第二部分和第二掺杂区域的第二部分之间的连接部分用作漏极输出; 以及形成在第一类型TFET垂直结构和第二类型TFET垂直结构之间的U形栅极结构。

    LDPC codes and expansion method
    55.
    发明授权
    LDPC codes and expansion method 有权
    LDPC码和扩展方法

    公开(公告)号:US08281213B1

    公开(公告)日:2012-10-02

    申请号:US12852817

    申请日:2010-08-09

    IPC分类号: H03M13/00

    摘要: A multiple-input multiple-output (MIMO) transmitter including a scrambler and a forward error correction encoder. The scrambler is configured to receive user data and generate scrambled data in response to the user data. The forward error correction encoder is configured to generate encoded data, in response to the scrambled data, using a low density parity check (LDPC) matrix, wherein the LDPC matrix is derived from a specified base matrix.

    摘要翻译: 一种包括扰频器和前向纠错编码器的多输入多输出(MIMO)发射机。 加扰器被配置为接收用户数据并响应于用户数据产生加扰数据。 前向纠错编码器被配置为使用低密度奇偶校验(LDPC)矩阵来响应于加扰的数据生成编码数据,其中从指定的基本矩阵导出LDPC矩阵。

    Method and Terminal for Channel State Information Feedback
    56.
    发明申请
    Method and Terminal for Channel State Information Feedback 有权
    渠道状态信息反馈的方法和终端

    公开(公告)号:US20120224652A1

    公开(公告)日:2012-09-06

    申请号:US13505866

    申请日:2011-08-01

    IPC分类号: H04B15/00 H04B1/02

    CPC分类号: H04B7/0626 H04B7/0639

    摘要: The present invention discloses a method and terminal for feeding back channel status information, including: when the channel status information is fed back on the physical uplink control channel, code words contained in the used codebook CPUCCH (r) with a layer number or rank being r is a subset of the code words contained in the codebook CPUSCH (r) with a layer number or rank being r in the overall codebook defined in the LTE-A; wherein, the CPUCCH (r) is a single codebook or a single codebook equivalent to dual codebooks; and the CPUSCH (r) is a single codebook or a single codebook equivalent to the dual codebooks; and the single codebook equivalent to the dual codebooks means that the actually used codebook is an actually defined single codebook, however, 2 pre-coding matrix identifiers are required to determine the codebook of the code words therein for an established r. The method described by the present invention can ensure the precision of the PMI feedback under the limited overhead, make the CSI feedback on the PUCCH still be able to more effectively support the pre-coding technology and have good compatibility with the feedback on the PUSCH.

    摘要翻译: 本发明公开了一种用于反馈信道状态信息的方法和终端,包括:当在物理上行链路控制信道上反馈信道状态信息时,包含在具有层号或级别的所使用码本CPUCCH(r)中的码字是 r是在LTE-A中定义的整个码本中的层号或等级为r的码本CPUSCH(r)中包含的码字的子集; 其中,CPUCCH(r)是与双码本相当的单码本或单码本; 并且CPUSCH(r)是与双码本相当的单个码本或单个码本; 与双码本相当的单码本意味着实际使用的码本是实际定义的单码本,然而,需要2个预编码矩阵标识符来确定已建立的r中的码字的码本。 本发明描述的方法可以在有限的开销下保证PMI反馈的精度,使得PUCCH上的CSI反馈能够更有效地支持预编码技术,并且与PUSCH上的反馈具有良好的兼容性。

    Monoclonal antibodies against activated protein C
    58.
    发明授权
    Monoclonal antibodies against activated protein C 有权
    活化蛋白C的单克隆抗体

    公开(公告)号:US08153766B2

    公开(公告)日:2012-04-10

    申请号:US12257706

    申请日:2008-10-24

    申请人: Jun Xu Charles Esmon

    发明人: Jun Xu Charles Esmon

    IPC分类号: C07K16/24

    摘要: The present invention provides monoclonal antibodies that selectively bind to and inhibit activated protein C without binding to or inhibiting unactivated protein C. Other antibodies inhibit both activated protein C and activation of unactivated protein C. Methods of treatment employing these antibodies are described herein as are methods of screening for and detecting these antibodies.

    摘要翻译: 本发明提供了选择性结合并抑制活化的蛋白C而不结合或抑制未活化蛋白C的单克隆抗体。其他抗体抑制活化的蛋白C和未活化蛋白C的活化。使用这些抗体的治疗方法在本文中被描述为方法 的筛选和检测这些抗体。

    MOS TRANSISTOR STRUCTURE WITH IN-SITU DOPED SOURCE AND DRAIN AND METHOD FOR FORMING THE SAME
    60.
    发明申请
    MOS TRANSISTOR STRUCTURE WITH IN-SITU DOPED SOURCE AND DRAIN AND METHOD FOR FORMING THE SAME 有权
    具有现场输入源和漏极的MOS晶体管结构及其形成方法

    公开(公告)号:US20120032231A1

    公开(公告)日:2012-02-09

    申请号:US13132768

    申请日:2011-01-19

    申请人: Jing Wang Lei Guo Jun Xu

    发明人: Jing Wang Lei Guo Jun Xu

    IPC分类号: H01L29/772 H01L21/336

    摘要: A MOS transistor structure with an in-situ doped source and/or drain and a method for forming the same are provided. The method comprises steps of: providing a substrate; forming a high Ge content layer on the substrate; forming a gate stack on the high Ge content layer and forming a side wall of one or more layers on both sides of the gate stack; etching the high Ge content layer to form a source region and/or a drain region; and forming a source and/or a drain in the source region and/or the drain region respectively by a low-temperature selective epitaxy, and introducing a doping gas during the low-temperature selective epitaxy to heavily dope the source and/or the drain and to in-situ activate a doping element.

    摘要翻译: 提供具有原位掺杂源极和/或漏极的MOS晶体管结构及其形成方法。 该方法包括以下步骤:提供衬底; 在所述基板上形成高Ge含量层; 在高Ge含量层上形成栅极叠层,并在栅叠层的两侧形成一层或多层的侧壁; 蚀刻高Ge含量层以形成源区和/或漏区; 以及通过低温选择性外延分别在源区和/或漏区中形成源极和/或漏极,并且在低温选择性外延期间引入掺杂气体以使源极和/或漏极 并原位激活掺杂元素。