公开(公告)号：US4800531A

公开(公告)日：1989-01-24

申请号：US944784

申请日：1986-12-22

申请人： Sam Dehganpour ,  Perry H. Pelley, III

发明人： Sam Dehganpour ,  Perry H. Pelley, III

IPC分类号： G11C11/408 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4082

摘要： A DRAM has an input address buffer in which the first stage is a NOR gate. The output of the NOR gate is clocked to a latch which is preset to the slow condition of the NOR gate. The NOR gate is clocked separately from the clocking of the output of the NOR gate to the latch. A refresh control circuit has an output which is also clocked to the latch. The latch provides an internal address signal for selecting a word line. The internal address signal is representative of the output of the NOR gate when the DRAM is running a data cycle and is representative of the output of the refresh control circuit when the DRAM is running a refresh cycle.

摘要翻译： DRAM具有输入地址缓冲器，其中第一级是NOR门。 NOR门的输出被计时到一个锁存器，该锁存器预设为NOR门的慢速状态。 NOR门与NOR门的输出与锁存器的时钟分开计时。 刷新控制电路具有也被锁定到锁存器的输出。 锁存器提供用于选择字线的内部地址信号。 当DRAM正在运行数据周期时，内部地址信号表示NOR门的输出，并且当DRAM处于刷新周期时代表刷新控制电路的输出。