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316 条记录 (耗时 0.04 秒)

    Apparatus for vapor deposition
    52.
    发明授权
    Apparatus for vapor deposition 失效
    气相沉积装置

    公开(公告)号：US5223305A

    公开(公告)日：1993-06-29

    申请号：US698797

    申请日：1991-05-13

    申请人： Koichi Tanaka ,  Kousuke Terada ,  Katsushi Okibayashi ,  Akiyoshi Mikami ,  Masaru Yoshida ,  Shigeo Nakajima

    发明人： Koichi Tanaka ,  Kousuke Terada ,  Katsushi Okibayashi ,  Akiyoshi Mikami ,  Masaru Yoshida ,  Shigeo Nakajima

    IPC分类号： H05B33/10 ,  C23C16/18 ,  C23C16/44 ,  C23C16/448 ,  C23C16/455 ,  C23C16/46 ,  H01L21/205

    CPC分类号： C23C16/46 ,  C23C16/455

    摘要： An apparatus for vapor deposition including a vapor deposition section to which at least one semiconductor material supply passage and at least one alkoxide material supply passage are connected, first heating means provided for the vapor deposition section and capable of maintaining the temperature thereof higher than that of the alkoxide supply passage, second heating means provided for the semiconductor material supply passage and capable of maintaining the temperature thereof higher than that of the vapor deposition section, and third heating means provided for the alkoxide material supply passage and capable of maintaining the temperature thereof constant, and a process for continuously forming a multilayered film on a substrate.

    摘要翻译： 一种用于气相沉积的装置，包括连接至少一个半导体材料供应通道和至少一个醇盐材料供应通道的气相沉积部分，为蒸镀部设置的第一加热装置，并且能够将其温度保持在高于 所述醇盐供给路径，为半导体材料供给路设置的第二加热单元，其温度保持为高于蒸镀部的温度;以及第三加热单元，设置在所述醇盐材料供给路径上，能够保持其温度恒定 ，以及在基板上连续形成多层膜的工序。

    Circuit for testability
    54.
    发明授权
    Circuit for testability 失效
    电路可测性

    公开(公告)号：US5161160A

    公开(公告)日：1992-11-03

    申请号：US472382

    申请日：1990-02-01

    申请人： Toshiyuki Yaguchi ,  Koichi Tanaka

    发明人： Toshiyuki Yaguchi ,  Koichi Tanaka

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/22

    CPC分类号： G01R31/318558

    摘要： An evaluation facilitating circuit incorporated in a logic circuit having a plurality of functional blocks, includes: many scan register groups obtained by dividing many F/Fs provided in each functional block, many scan paths for scanning a plurality of test data used for input and output operations for the scan register groups, wherein a scan path is provided for each scan register group, and a decoder for designating the scan paths and controlling the input and output operations of test signals used for testing the scan register groups. A first scan register group in each functional group is composed of scan registers only used for the input operations to other functional blocks, a second scan register group is composed of scan registers only used for the output operations to other functional blocks and a third scan register group is composed of scan registers used for the input and output operations to the same functional block. Each scan path is connected to a common bus provided in the functional circuit. The common bus includes many signal lines through which the test data is transferred, and the scan path connected to a first scan register group is connected to a first pair of signal lines, the scan path connected to the second scan register group is connected to a second pair of signal lines, and the scan path connected to the third scan register group is connected to a third pair of signal lines.

    Electroluminescent device
    55.
    发明授权
    Electroluminescent device 失效
    电致发光器件

    公开(公告)号：US5087531A

    公开(公告)日：1992-02-11

    申请号：US442634

    申请日：1989-11-29

    申请人： Kousuke Terada ,  Akiyoshi Mikami ,  Kouji Taniguchi ,  Koichi Tanaka ,  Masaru Yoshida ,  Shigeo Nakajima

    发明人： Kousuke Terada ,  Akiyoshi Mikami ,  Kouji Taniguchi ,  Koichi Tanaka ,  Masaru Yoshida ,  Shigeo Nakajima

    IPC分类号： C09K11/57 ,  C09K11/88 ,  H05B33/10 ,  H05B33/14

    CPC分类号： H05B33/14 ,  C09K11/574 ,  C09K11/883 ,  H05B33/10 ,  Y10S428/917

    摘要： Disclosed is an electroluminescent device including a substrate and an electroluminescent film on the substrate wherein the electroluminescent film is composed of a II-VI group compound semiconductor matrix and an electroluminescent center element; the improvement being present in that the electroluminescent film has a crystal structure of a hexagonal system, and contains the electroluminescent center element in a concentration (Ci) of 0.5 to 4 at. % within a thickness of 0.2 micrometer from the side of the substrate and in a concentration (Cr) of 0.15 to 0.7 at. % at the residual portion, and Ci is larger than Cr, and the process for preparing the same.

    摘要翻译： 公开了一种电致发光器件，其在衬底上包括衬底和电致发光膜，其中电致发光膜由II-VI族化合物半导体衬底和电致发光中心元件构成; 存在的改进在于电致发光膜具有六方晶系的晶体结构，并且含有浓度（Ci）为0.5-4atm的电致发光中心元件。 的厚度为0.2微米，并且浓度（Cr）为0.15〜0.7at。 ％，并且C 1大于Cr，以及其制备方法。

    Truing device for hones
    57.
    发明授权
    Truing device for hones 失效
    修整设备用于骨骼

    公开(公告)号：US4811521A

    公开(公告)日：1989-03-14

    申请号：US113162

    申请日：1987-10-27

    申请人： Yoshio Nakae ,  Akiyo Kinoshita ,  Koichi Tanaka

    发明人： Yoshio Nakae ,  Akiyo Kinoshita ,  Koichi Tanaka

    IPC分类号： B24B33/10 ,  B24B5/00

    CPC分类号： B24B33/10

    摘要： A truing device that can form surfaces of hones, installed in a honing tool, into R-shapes (i.e. provided with rounded off edges or corners) with the same diameter as that of the honing tool or plane shapes. A truing tool is provided with a penetrating hole through which the honing tool is inserted and at least a part of an inner surface of the penetrating hole is a cylindrical surface having the same diameter as that of the honing tool and at least a part of said penetrating hole inner surface is provided with cutting edges for hone grinding. A tool holder housing the truing tool attachably and removably is held in a jig body of a tool holding device in a manner that the tool holder can shake within a range of three dimensional minute angles, thereby allowing said truing tool to smoothly follow movement of said honing tool during truing.

    摘要翻译： 一种修整装置，其可以安装在珩磨工具中的具有与珩磨工具或平面形状相同的直径的R形（即，设有圆形边缘或角部）的表面。 修整工具设置有穿孔，珩磨工具通过该孔穿入，并且穿透孔的内表面的至少一部分是具有与珩磨工具直径相同的直径的圆柱形表面，并且至少一部分所述 穿孔内表面设有切削刃，用于磨削磨削。 将修整工具以可拆卸的方式容纳并保持在工具夹持装置的夹具本体中的工具夹具能够在三维微小角度的范围内摇动工具夹持器，从而允许所述修整工具平稳地跟随所述工具夹持装置的运动 修整中的珩磨工具。

    Digital superimposed edge generation apparatus
    58.
    发明授权
    Digital superimposed edge generation apparatus 失效
    数字叠加边产生装置

    公开(公告)号：US4646154A

    公开(公告)日：1987-02-24

    申请号：US599614

    申请日：1984-04-03

    申请人： Nobutaka Shinohara ,  Shuji Hirakawa ,  Akihiko Minami ,  Koichi Tanaka

    发明人： Nobutaka Shinohara ,  Shuji Hirakawa ,  Akihiko Minami ,  Koichi Tanaka

    IPC分类号： H04N5/278 ,  G06T17/00 ,  G09G5/36 ,  G09G5/377 ,  H04N5/262 ,  H04N5/445

    CPC分类号： G06T17/00 ,  H04N5/2622 ,  H01L2224/29 ,  H01L2224/29298 ,  H01L2924/00011 ,  H01L2924/00013

    摘要： A vertical edge width calculation circuit 31 has a plurality of series-connected delay circuits 31a to 31h each having a one-horizontal period delay time. A horizontal edge width calculation circuit has a plurality of 1-pixel delay circuits 32a to 32h corresponding to the edge width. A horizontal distance between an input digital superimpose key signal and a raster position is calculated in accordance with the calculated vertical distance, that is, the edge width. In accordance with the calculated vertical and horizontal distances, a detection circuit 34 detects as a true Euclidean distance a minimum value among a plurality of Euclidean distances between the digital superimpose key signal and the raster position which are stored in ROMs 33.sub.0 to 33.sub.5.

    摘要翻译： PCT No.PCT / JP83 / 00204 Sec。 1984日期1984年4月3日 102（e）1984年4月3日，PCT提交1983年6月24日。垂直边缘宽度计算电路31具有多个串联连接的延迟电路31a至31h，每个延迟电路具有一个水平周期的延迟时间。 水平边缘宽度计算电路具有对应于边缘宽度的多个1像素延迟电路32a至32h。 根据计算出的垂直距离，即边缘宽度，计算输入数字叠加键信号和光栅位置之间的水平距离。 根据计算出的垂直和水平距离，检测电路34将存储在ROM 330至335中的数字叠加键信号和光栅位置之间的多个欧几里德距离中的最小值检测为真欧几里德距离。