公开(公告)号：US20070294327A1

公开(公告)日：2007-12-20

申请号：US11894393

申请日：2007-08-20

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G06F7/58

CPC分类号： G06F7/584 ,  G06F2207/583 ,  H03K3/84

摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.

公开(公告)号：US06557129B1

公开(公告)日：2003-04-29

申请号：US09619988

申请日：2000-07-20

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G01R3128

CPC分类号： G01R31/318547

摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

公开(公告)号：US06539409B2

公开(公告)日：2003-03-25

申请号：US09957701

申请日：2001-09-18

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G06F102

CPC分类号： G06F7/584 ,  G06F2207/583 ,  H03K3/84

摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.

公开(公告)号：US08832512B2

公开(公告)日：2014-09-09

申请号：US13049829

申请日：2011-03-16

申请人： Dariusz Czysz ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Janusz Rajski ,  Przemyslaw Szczerbicki ,  Jerzy Tyszer

发明人： Dariusz Czysz ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Janusz Rajski ,  Przemyslaw Szczerbicki ,  Jerzy Tyszer

IPC分类号： G06F11/00

CPC分类号： G06F11/079

摘要： Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.

摘要翻译： 公开了涉及用于具有冲突的测试立方体的确定性聚类的功率感知测试应用的方法，装置和系统的代表性实施例。 所公开的技术的实施例可以用于产生低切换父模式，以降低测试集成电路期间的功耗。 可以通过产生低切换控制模式来进一步降低功耗。

公开(公告)号：US08533547B2

公开(公告)日：2013-09-10

申请号：US13013712

申请日：2011-01-25

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

公开(公告)号：US20110231721A1

公开(公告)日：2011-09-22

申请号：US13049829

申请日：2011-03-16

申请人： DARIUSZ CZYSZ ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Janusz Rajski ,  Przemyslaw Szczerbicki ,  Jerzy Tyszer

发明人： DARIUSZ CZYSZ ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Janusz Rajski ,  Przemyslaw Szczerbicki ,  Jerzy Tyszer

IPC分类号： G06F11/00 ,  G06F1/32

CPC分类号： G06F11/079

摘要： Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.

摘要翻译： 公开了涉及用于具有冲突的测试立方体的确定性聚类的功率感知测试应用的方法，装置和系统的代表性实施例。 所公开的技术的实施例可以用于产生低切换父模式，以降低测试集成电路期间的功耗。 可以通过产生低切换控制模式来进一步降低功耗。

公开(公告)号：US07805649B2

公开(公告)日：2010-09-28

申请号：US12396377

申请日：2009-03-02

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

摘要翻译： 一种在确定性测试环境中压缩包含未知值或多个故障效应的测试响应的方法和装置。 所提出的选择性压实机采用具有用于选择性地将测试响应传递给压实机的选择电路的线性压实机。 在一个实施例中，门控逻辑由控制寄存器，解码器和标志寄存器控制。 该电路结合任何常规的并行测试响应压缩方案，允许控制电路选择性地使所需扫描链的串行输出以特定时钟速率馈送到并联压实机。 第一个标志寄存器确定是否启用所有或只有一些扫描链输出并通过压实器馈送。 第二个标志寄存器确定选择器寄存器选择的扫描链是否启用，所有其他扫描链是禁用的，还是禁用所选扫描链，并启用所有其他扫描链。 其他实施例允许对可变数目的扫描链输出的选择性掩蔽。

公开(公告)号：US20100229060A1

公开(公告)日：2010-09-09

申请号：US12718813

申请日：2010-03-05

申请人： GRZEGORZ MRUGALSKI ,  Nilanjan Mukherjee ,  Janusz Rajski ,  Dariusz Czysz ,  Jerzy Tyszer

发明人： GRZEGORZ MRUGALSKI ,  Nilanjan Mukherjee ,  Janusz Rajski ,  Dariusz Czysz ,  Jerzy Tyszer

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/31921 ,  G01R31/318547

摘要： The test data compression scheme is based on deterministic vector clustering. Test cubes that feature many similar specified bits are merged into a parent pattern in the presence of conflicts. The parent pattern along with a control pattern and incremental patterns representing conflicting bits are encoded efficiently. A tri-modal decompressor may be used to decompress the test data.

摘要翻译： 测试数据压缩方案基于确定性向量聚类。 在存在冲突的情况下，具有许多类似指定位的测试立方体将合并到父模式中。 父模式以及表示冲突位的控制模式和增量模式被有效地编码。 三模式解压缩器可用于解压缩测试数据。

公开(公告)号：US20090183041A1

公开(公告)日：2009-07-16

申请号：US12352994

申请日：2009-01-13

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318335 ,  G01R31/31813 ,  G01R31/318547

摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear feedbackstate machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.

摘要翻译： 在测试电路中将测试图案应用于扫描链的方法。 该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。 取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。 执行解压缩的电路包括解压缩器，例如适于接收压缩的比特测试模式的线性反馈状态机。 解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。 电路还包括用于测试电路逻辑的扫描链，扫描链耦合到解压缩器并且适于接收解压缩的测试图案。

公开(公告)号：US20090177933A1

公开(公告)日：2009-07-09

申请号：US12402880

申请日：2009-03-12

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318335 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547

摘要： A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

摘要翻译： 微芯片上的新型解压缩器/ PRPG对芯片上的电路不足测试的确定性测试模式进行伪随机测试模式生成和解压缩。 解压缩器/ PRPG有两个操作阶段。 在伪随机阶段，解压缩器/ PRPG生成伪随机测试图案，其应用于被测电路中的扫描链。 在确定性阶段，将外部测试仪的压缩确定性测试模式应用于解压缩器/ PRPG。 在通过解压缩器/ PRPG计时到扫描链中时，模式被解压缩。 因此，解压缩器/ PRPG提供比简单PRPG更好的故障覆盖，但是没有完整的完整指定的确定性测试模式的成本。