公开(公告)号：US06718433B1

公开(公告)日：2004-04-06

申请号：US10243076

申请日：2002-09-12

申请人： Jose Pio Pereira

发明人： Jose Pio Pereira

IPC分类号： G06F1202

CPC分类号： G11C15/00

摘要： A plurality of match and priority encoding logic (MPL) circuits are connected in a chain. Each MPL circuit includes a plurality of input terminals coupled to an associated set of match lines from a content addressable memory (CAM) array, an index input port to receive an input index from a previous MPL circuit, an index output port to provide an output index to a next MPL circuit, and a select terminal to receive a select signal.

摘要翻译： 在链中连接多个匹配和优先编码逻辑（MPL）电路。 每个MPL电路包括从内容可寻址存储器（CAM）阵列耦合到相关联的匹配线组的多个输入端子，用于从先前MPL电路接收输入索引的索引输入端口，以提供输出的索引输出端口 索引到下一个MPL电路，以及选择端子来接收选择信号。

公开(公告)号：US06687785B1

公开(公告)日：2004-02-03

申请号：US09590775

申请日：2000-06-08

申请人： Jose Pio Pereira

发明人： Jose Pio Pereira

IPC分类号： G06F1200

CPC分类号： G11C15/04 ,  G11C15/00

摘要： A method and apparatus that may be used to disable one or more defective CAM blocks, and to selectively re-assign priority between the remaining enabled CAM blocks. In one embodiment, each CAM block includes an array of CAM cells organized in a number of rows and columns, where each row has a match line to indicate match conditions therein during a compare operation. Each block also includes a block priority encoder coupled to the number of match lines and having an output to provide a row index of a row that stores data that matches comparand data. The row indexes from the CAM blocks are provided to a main priority encoder that stores a dynamic block index for each of the plurality of CAM blocks. The main priority encoder combines each row index with a corresponding block index to generate a device index for each CAM block. The main priority encoder may re-assign priority between the plurality of CAM blocks by manipulating the dynamic block indexes.

摘要翻译： 可以用于禁用一个或多个有缺陷的CAM块的方法和装置，并且在剩余使能的CAM块之间选择性地重新分配优先级。 在一个实施例中，每个CAM块包括以多个行和列组织的CAM单元的阵列，其中每行具有匹配线，以在比较操作期间指示其中的匹配条件。 每个块还包括耦合到匹配线数量并具有输出以提供存储与比较数据匹配的数据的行的行索引的块优先级编码器。 来自CAM块的行索引被提供给主要优先级编码器，其存储多个CAM块中的每一个的动态块索引。 主要优先级编码器将每个行索引与相应的块索引组合，以生成每个CAM块的设备索引。 主要优先级编码器可以通过操纵动态块索引来在多个CAM块之间重新分配优先级。

公开(公告)号：US06252789B1

公开(公告)日：2001-06-26

申请号：US09594203

申请日：2000-06-14

申请人： Jose Pio Pereira ,  Varadarajan Srinivasan

发明人： Jose Pio Pereira ,  Varadarajan Srinivasan

IPC分类号： G11C1500

CPC分类号： G06F17/30982 ,  G11C15/00

摘要： A CAM system for storing a data word chain having a sequence of one or more data words stored in one or more rows of CAM cells. For one embodiment, the CAM system includes rows of CAM cells each for storing a data word in a data word chain, match lines, and width expansion logic circuits each having a plurality of control inputs for receiving a plurality of control signals. The width expansion logic circuits are interconnected and determine when and how match results are communicated to a priority encoder and to each other. The control signals are for determining the operation of the width expansion logic circuits and for indicating when a first data word, a continuing data word, and a last data word of the data word chain are provided for comparison with the rows of CAM cells. The continuing data word is a data word between the first and last data word in the data word chain. For one embodiment, the control signals are generated by an instruction decoder in response to decoding separate instructions for comparing the first data word, a continuing data word, and the last data word of a data word chain. Each row of CAM cells may also include classification information or control bits that indicate the data word chain or the place of a data word in the data word chain. For one embodiment, the CAM system can store and operate on data word chains of different lengths.

摘要翻译： 一种用于存储具有存储在一个或多个CAM单元格行中的一个或多个数据字的序列的数据字链的CAM系统。 对于一个实施例，CAM系统包括各个CAM单元行，用于存储数据字链中的数据字，匹配线和宽度扩展逻辑电路，每个具有用于接收多个控制信号的多个控制输入。 宽度扩展逻辑电路互连，并确定何时以及如何将结果传递给优先编码器和彼此。 控制信号用于确定宽度扩展逻辑电路的操作，并且用于指示何时提供数据字链的第一数据字，连续数据字和最后数据字以与CAM单元的行进行比较。 持续数据字是数据字链中第一个和最后一个数据字之间的一个数据字。 对于一个实施例，响应于解码用于比较数据字链的第一数据字，连续数据字和最后数据字的分离指令，由指令解码器产生控制信号。 CAM单元的每一行也可以包括指示数据字链中的数据字链或数据字的位置的分类信息或控制位。 对于一个实施例，CAM系统可以存储和操作不同长度的数据字链。

公开(公告)号：US07325091B2

公开(公告)日：2008-01-29

申请号：US10855580

申请日：2004-05-26

申请人： Jose Pio Pereira

发明人： Jose Pio Pereira

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G11C15/00 ,  G11C15/04

摘要： A CAM device having a plurality of CAM blocks includes circuitry to disable one or more defective CAM blocks, and to selectively translate address space in the disabled CAM blocks to the remaining enabled CAM blocks. In one embodiment, each CAM block is coupled to a corresponding block select circuit and to an address translation circuit. Each block select circuit provides a select signal to a corresponding CAM block to selectively enable or disable the CAM block. The address translation circuit includes logic that translates address space from disabled (e.g., defective) CAM blocks to enabled (e.g., non-defective) CAM blocks. During read and write operations, an address to access a row in a first of the CAM blocks is received into the address translation logic. If the first CAM block is disabled, the address translation logic translates the address to access a row in a second of the CAM blocks. Conversely, if the first CAM block is enabled, the address translation logic facilitates access to the row in the first CAM block.

摘要翻译： 具有多个CAM块的CAM设备包括用于禁用一个或多个有缺陷的CAM块的电路，并且将禁用的CAM块中的地址空间选择性地转换为剩余的启用的CAM块。 在一个实施例中，每个CAM块耦合到对应的块选择电路和地址转换电路。 每个块选择电路向对应的CAM块提供选择信号以选择性地启用或禁用CAM块。 地址转换电路包括将地址空间从禁用（例如，有缺陷的）CAM块转换为启用（例如，无缺陷）的CAM块的逻辑。 在读取和写入操作期间，访问第一个CAM块中的行的地址被接收到地址转换逻辑中。 如果第一个CAM块被禁用，则地址转换逻辑将地址转换为访问第二个CAM块中的一行。 相反，如果第一CAM块被使能，则地址转换逻辑便于访问第一CAM块中的行。

公开(公告)号：US06813680B1

公开(公告)日：2004-11-02

申请号：US09594209

申请日：2000-06-14

申请人： Jose Pio Pereira

发明人： Jose Pio Pereira

IPC分类号： G06F1200

CPC分类号： G11C15/04 ,  G11C15/00

摘要： A method and apparatus for loading comparand data into a content addressable memory system. For one embodiment, the CAM system includes a CAM array, a comparand register and select logic. The CAM array includes a plurality of rows of CAM cells each segmented into a plurality of row segments each having a plurality of CAM cells. The comparand register includes a plurality of segments for storing comparand data for comparing with data stored in the CAM array. The select logic selectively enables each segment of the comparand register to store a portion of the comparand data in response to configuration information. The configuration information is indicative of the width and depth of the CAM array. The select logic may also enable each segment of the comparand register to simultaneously load the comparand data.

摘要翻译： 一种用于将比较数据加载到内容可寻址存储器系统中的方法和装置。 对于一个实施例，CAM系统包括CAM阵列，比较寄存器和选择逻辑。 CAM阵列包括多行CAM单元，每行分割成多个行段，每行具有多个CAM单元。 比较寄存器包括用于存储用于与存储在CAM阵列中的数据进行比较的比较数据的多个段。 选择逻辑选择性地使比较寄存器的每个段响应于配置信息存储比较数据的一部分。 配置信息表示CAM阵列的宽度和深度。 选择逻辑还可以使比较寄存器的每个段同时加载比较数据。

公开(公告)号：US06799243B1

公开(公告)日：2004-09-28

申请号：US09594201

申请日：2000-06-14

申请人： Jose Pio Pereira ,  Varadarajan Srinivasan

发明人： Jose Pio Pereira ,  Varadarajan Srinivasan

IPC分类号： G06F1200

CPC分类号： G11C15/04 ,  G11C15/00

摘要： A method and apparatus for detecting a match in an intra-row configurable CAM system. For one embodiment, the CAM system includes a CAM array and match flag logic. The CAM array includes a plurality of rows of CAM cells each segmented into a plurality of row segments having a plurality of CAM cells coupled to a corresponding match line segment. The match flag logic is coupled to the match line segments and determines when first comparand data matches data stored in at least one of the row segments in response to first configuration information, and determines when second comparand data matches data stored in at least one group of row segments in response to second configuration information. The first configuration information is indicative of a first width and depth configuration of the CAM array, and the second configuration information is indicative of a second width and depth configuration of the CAM array.

摘要翻译： 一种用于检测行内可配置CAM系统中的匹配的方法和装置。 对于一个实施例，CAM系统包括CAM阵列和匹配标志逻辑。 CAM阵列包括多个CAM单元行，每一行分割成具有耦合到对应匹配线段的多个CAM单元的多个行段。 匹配标志逻辑被耦合到匹配线段，并且响应于第一配置信息确定第一对比数据何时匹配存储在至少一个行段中的数据，并且确定何时第二比较数据匹配存储在至少一组 响应于第二配置信息的行段。 第一配置信息指示CAM阵列的第一宽度和深度配置，并且第二配置信息指示CAM阵列的第二宽度和深度配置。

公开(公告)号：US06795892B1

公开(公告)日：2004-09-21

申请号：US09594202

申请日：2000-06-14

申请人： Jose Pio Pereira ,  Varadarajan Srinivasan

发明人： Jose Pio Pereira ,  Varadarajan Srinivasan

IPC分类号： G06F1200

CPC分类号： G11C15/00 ,  G11C15/04

摘要： A method and apparatus for determining a match address in an intra-row configurable CAM system. For one embodiment, the CAM system includes a CAM array and priority encoding circuitry. The CAM system includes a plurality of rows of CAM cells each segmented into a plurality of row segments having a plurality of CAM cells coupled to a corresponding match line segment. The priority encoding circuitry is coupled to the match line segments and has inputs to receive configuration information indicative of a width and depth configuration of the CAM array. The priority encoding circuitry is configured to generate a first match address in the CAM array corresponding to a row segment that stores data matching first comparand data in response to first configuration information, and is further configured to generate a second match address in the CAM array corresponding to a group of row segments that store data matching second comparand data in response to the second configuration information. The first and second configuration information correspond to different width and depth configurations.

摘要翻译： 一种用于确定行内可配置CAM系统中的匹配地址的方法和装置。 对于一个实施例，CAM系统包括CAM阵列和优先级编码电路。 CAM系统包括多行CAM单元，每行分割成具有耦合到对应匹配线段的多个CAM单元的多个行段。 优先编码电路耦合到匹配线段并具有用于接收指示CAM阵列的宽度和深度配置的配置信息的输入。 优先级编码电路被配置为在对应于存储与第一配置信息匹配的第一比较数据的数据的行段相对应的CAM阵列中生成第一匹配地址，并且还被配置为在对应的CAM阵列中生成第二匹配地址 涉及一组行段，其响应于第二配置信息存储与第二比较数据匹配的数据。 第一和第二配置信息对应于不同的宽度和深度配置。

公开(公告)号：US06317350B1

公开(公告)日：2001-11-13

申请号：US09595850

申请日：2000-06-16

申请人： Jose Pio Pereira ,  Varadarajan Srinivasan

发明人： Jose Pio Pereira ,  Varadarajan Srinivasan

IPC分类号： G11C1500

CPC分类号： G11C15/00

摘要： A method and apparatus hierarchically cascades a number of memory devices to achieve a balance between the number of match flag inputs and the time required to generate the system match flag. In some embodiments, the number of match inputs required for each cascaded device and the time required to generate a system match flag are each logarithmically related to the number of cascaded devices. In one embodiment, an m-level hierarchy of groups are defined for up to n memory devices, where m=log2n and m is an integer greater than 2. The first hierarchy is defined as including n/2 groups of 2 memory devices, the second hierarchy is defined as including n/4 groups of 4 memory devices, and so on, until a final hierarchy of one group is defined. Each group in a given hierarchical level includes a pair of groups from the preceding hierarchical level. At each hierarchical level, the match flag generated by the first of the group's pair may be provided to each of the CAM devices in the second of the group's pair. In other embodiments, at each hierarchical level, the match flag(s) generated by devices in the first of the pair defined in the previous hierarchical are selectively provided to devices in the second of the pair defined in the previous hierarchical level.

摘要翻译： 一种方法和装置分级级联多个存储器件以实现匹配标志输入的数量与产生系统匹配标志所需的时间之间的平衡。 在一些实施例中，每个级联设备所需的匹配输入的数量和产生系统匹配标志所需的时间与级联设备的数量对数地相关。 在一个实施例中，为多达n个存储器件定义组的m级层级，其中m = log2n，m是大于2的整数。第一层次被定义为包括2组存储器件的n / 2组， 第二层次被定义为包含4组存储器件的n / 4组，等等​​，直到定义了一个组的最终层次结构。 给定分层级别中的每个组包括来自上一级别级别的一对组。 在每个分层级别，可以将该组对中的第一组生成的匹配标志提供给组对中的第二组中的每个CAM设备。 在其他实施例中，在每个分层级别，由先前分级中定义的对中的第一对中由设备生成的匹配标志被选择性地提供给在先前层级中定义的对中的第二对中的设备。