公开(公告)号：US20050246475A1

公开(公告)日：2005-11-03

申请号：US11173640

申请日：2005-07-01

申请人： Joseph Ervin

发明人： Joseph Ervin

IPC分类号： G06F13/40 ,  G06F13/36

CPC分类号： G06F13/4045

摘要： A large multimaster I2C bus system is partitioned into smaller bus segments. The bus segments are connected by bridges that isolate the segments and direct selected transactions and commands between the segments. By programming address bitmaps that are internal to each bridge, transactions can pass through the bridges so that the various bus segments appear to be one logical bus. Because each bridge implements address filtering so that transactions are selectively forwarded from one side of the bridge to the other based on the contents of an internal address bitmap, I2C slave addresses can be arbitrarily populated on either side of the bridge. Duplicate I2C slave addresses can be also used on different segments of a single logical I2C bus system. Masters on one segment can reach devices connected to the same bus segment and can also reach devices with duplicate addresses on other bus segments by using a tunnel command addressed to a bridge.

摘要翻译： 一个大的多主机I <2> C总线系统被划分成较小的总线段。 总线段通过隔离段的桥连接，并在段之间直接选择事务和命令。 通过编程每个桥接器内部的地址位图，事务可以通过桥接器，使得各种总线段看起来是一条逻辑总线。 因为每个桥都实现了地址过滤，所以根据内部地址位图的内容，事务从桥的一侧被选择性地转发到另一侧，因此可以任意地在任一侧填充从属地址 的桥梁。 重复的I <2> 2个从机地址也可以用在单个逻辑I 2 C总线系统的不同段上。 一个分段上的主机可以到达连接到同一总线段的设备，并且还可以通过使用寻址到桥接器的隧道命令来到达其他总线段上具有重复地址的设备。

公开(公告)号：US06226703B1

公开(公告)日：2001-05-01

申请号：US09188847

申请日：1998-11-09

申请人： Joseph Ervin ,  Jonathan Crowell

发明人： Joseph Ervin ,  Jonathan Crowell

IPC分类号： G06F1340

CPC分类号： G06F13/4054

摘要： An apparatus is provided for reducing read latency for an I/O device residing on a bus having a short read latency timeout period. The apparatus includes a I/O bridge on an I/O bus having a longer read latency timeout which modifies read transactions into two separate transactions, a write transaction to the same address requested by the read transaction which will force a write-back if the address hits in the CPU's write-back cache, and then performing the read transaction which is performed after a predetermined period of time following initiation of the write transaction. This removes the possibility of a device on the I/O bus having a short read latency timeout period from exceeding it's read latency timeout limit.

摘要翻译： 提供了一种用于减少驻留在具有短读延迟超时周期的总线上的I / O设备的读延迟的装置。 该装置包括I / O总线上的I / O桥，其具有较长的读取等待时间超时，该读取延迟超时将读取事务修改为两个单独的事务，对由读取事务请求的同一地址进行写入事务，这将强制回写，如果 在CPU的写回缓存中的地址命中，然后执行在写入事务开始之后的预定时间段之后执行的读事务。 这消除了I / O总线上的器件具有超过其读延迟超时限制的短读延迟超时周期的可能性。

公开(公告)号：US5862358A

公开(公告)日：1999-01-19

申请号：US856032

申请日：1997-05-14

申请人： Joseph Ervin ,  Jonathan Crowell

发明人： Joseph Ervin ,  Jonathan Crowell

IPC分类号： G06F13/40 ,  G06F13/14

CPC分类号： G06F13/4054

摘要： An apparatus is provided for reducing read latency for an I/O device residing on a first bus having a first, short read latency timeout period. The apparatus includes a I/O bridge on a second bus having a second, longer read latency timeout compared to that of first bus which modifies read transactions into two separate transactions. A first transaction is a write transaction to the same address requested by the read transaction. This transaction forces a write-back if the address hits in a CPU's write-back cache. Thereafter the read transaction is performed after a predetermined period of time following initiation of the write transaction. This removes the possibility of a device on the first bus having a short read latency timeout period from exceeding it's read latency timeout limit.

摘要翻译： 提供了一种用于减少驻留在具有第一短读延迟超时周期的第一总线上的I / O设备的读延迟的装置。 该装置包括在第二总线上的I / O桥，其具有与将第一总线相比较的更长的读延迟超时，其将读取事务修改为两个单独的事务。 第一个事务是对读取事务请求的同一地址的写入事务。 如果地址在CPU的回写缓存中，该事务强制回写。 此后，在写入事务开始之后的预定时间段之后执行读取事务。 这消除了在第一总线上的设备具有超过其读延迟超时限制的短读延迟超时周期的可能性。