利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

69 条记录 (耗时 0.025 秒)

    Operating System of Liquefied Natural Gas Ship for Subcooling and Liquefying Boil-Off Gas
    51.
    发明申请
    Operating System of Liquefied Natural Gas Ship for Subcooling and Liquefying Boil-Off Gas 有权
    用于过冷和液化沸腾气体的液化天然气船舶操作系统

    公开(公告)号：US20100139316A1

    公开(公告)日：2010-06-10

    申请号：US12688411

    申请日：2010-01-15

    申请人： Hyung-Su An ,  Nam-Su Kim ,  Jin-Yeol Yun ,  Hyun-Jin Kim ,  Hyun-Ki Park

    发明人： Hyung-Su An ,  Nam-Su Kim ,  Jin-Yeol Yun ,  Hyun-Jin Kim ,  Hyun-Ki Park

    IPC分类号： F25J1/00 ,  F17C3/08

    CPC分类号： F25J1/0245 ,  B63B25/16 ,  F25J1/0025 ,  F25J1/0045 ,  F25J1/005 ,  F25J1/0072 ,  F25J1/0208 ,  F25J1/0277 ,  F25J2205/02 ,  F25J2205/30 ,  F25J2220/62 ,  F25J2230/08 ,  F25J2230/60 ,  F25J2245/02 ,  F25J2245/42

    摘要： An operating system of a liquefied natural gas ship for performing sub-cooled liquefaction of boil-off gas includes a boil-off gas compressor, a cryogenic heat exchanger connected to a refrigerator system, and a first check valve and a first pressure control valve, installed in a pipe between a liquefied natural gas phase separator and a gas combustion unit, and a second check valve and a second pressure control valve, installed in a parallel pipe connected to the pipe in parallel. The parallel pipe is connected to a pipe between the boil-off gas compressor and the cryogenic heat exchanger such that boil-off gas is supplied to an upper vapor region of the liquefied natural gas phase separator. Thus, pressure and level of the liquefied natural gas phase separator are stably controlled. Power consumption is effectively reduced, and economical efficiency is achieved by stable operating pressure and level of the liquefied natural gas phase separator.

    摘要翻译： 液化天然气船的操作系统，用于进行冷却液化的蒸发气体包括：蒸发气体压缩机，连接到冰箱系统的低温热交换器，以及第一止回阀和第一压力控制阀， 安装在液化天然气分离器和气体燃烧单元之间的管道中，以及安装在并联管道上并联的第二止回阀和第二压力控制阀。 并联管连接到蒸发气体压缩机和低温热交换器之间的管道，使得蒸发气体被供应到液化天然气分离器的上部蒸汽区域。 因此，稳定地控制液化天然气分离器的压力和液位。 有效降低功耗，通过液化天然气分离器的稳定运行压力和水平实现经济效益。

    Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device
    52.
    发明授权
    Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device 有权
    在双泵浦地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法

    公开(公告)号：US07656742B2

    公开(公告)日：2010-02-02

    申请号：US12128464

    申请日：2008-05-28

    申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

    发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

    IPC分类号： G11C8/00

    CPC分类号： G06F12/02 ,  G11C7/1078 ,  G11C7/109

    摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

    摘要翻译： 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

    Small swing signal receiver for low power consumption and semiconductor device including the same
    53.
    发明授权
    Small swing signal receiver for low power consumption and semiconductor device including the same 有权
    用于低功耗的小型摆动信号接收器和包括它的半导体器件

    公开(公告)号：US07463072B2

    公开(公告)日：2008-12-09

    申请号：US11566651

    申请日：2006-12-04

    申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

    发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

    IPC分类号： H03B1/00

    CPC分类号： H03K19/0013 ,  H03K19/018521

    摘要： A circuit including a voltage boost circuit coupled to a first node and a second node, and configured to apply a boosted first node voltage to the second node; and an inverter circuit coupled to the first node, the second node, and a third node, and configured to generate a signal on the third node in response to the signals on the first node and the second node.

    摘要翻译： 一种电路，包括耦合到第一节点和第二节点的升压电路，并且被配置为将升压的第一节点电压施加到所述第二节点; 以及反相器电路，其耦合到所述第一节点，所述第二节点和第三节点，并且被配置为响应于所述第一节点和所述第二节点上的信号而在所述第三节点上生成信号。

    Methods of generating internal clock signals from external clock signals and of measuring the frequency of external clock signals and related frequency measuring circuits and semiconductor memory devices
    54.
    发明授权
    Methods of generating internal clock signals from external clock signals and of measuring the frequency of external clock signals and related frequency measuring circuits and semiconductor memory devices 失效
    从外部时钟信号产生内部时钟信号以及测量外部时钟信号和相关频率测量电路和半导体存储器件的频率的方法

    公开(公告)号：US07274185B2

    公开(公告)日：2007-09-25

    申请号：US11184616

    申请日：2005-07-19

    申请人： Hyun-Jin Kim

    发明人： Hyun-Jin Kim

    IPC分类号： G11C27/00 ,  H03D13/00 ,  G01R23/02

    CPC分类号： G11C7/22 ,  G11C7/222

    摘要： Pursuant to certain embodiments of the present invention, methods of generating an internal clock signal in a semiconductor memory device are provided in which the frequency of an external clock signal is measured. A CAS latency value of the semiconductor memory device is automatically set based at least in part on the measured frequency of the external clock signal. The automatically set CAS latency value is then used to generate the internal clock signal from the external clock signal. In these methods, the delay of a delay lock loop of the semiconductor memory device may be based at least in part on the automatically set CAS latency value. The internal clock signal may be generated from the external clock signal using the delay lock loop. Circuits and methods for measuring the frequency of the external clock signal are also provided.

    摘要翻译： 根据本发明的某些实施例，提供了在半导体存储器件中产生内部时钟信号的方法，其中测量外部时钟信号的频率。 至少部分地基于所测量的外部时钟信号的频率来自动设置半导体存储器件的CAS延迟值。 然后，自动设置CAS延迟值用于从外部时钟信号生成内部时钟信号。 在这些方法中，半导体存储器件的延迟锁定环的延迟可以至少部分地基于自动设置的CAS等待时间值。 可以使用延迟锁定环从外部时钟信号产生内部时钟信号。 还提供了用于测量外部时钟信号频率的电路和方法。

    Frequency measuring circuits including charge pumps and related memory devices and methods
    55.
    发明授权
    Frequency measuring circuits including charge pumps and related memory devices and methods 失效
    频率测量电路包括电荷泵和相关的存储器件和方法

    公开(公告)号：US07219026B2

    公开(公告)日：2007-05-15

    申请号：US11031104

    申请日：2005-01-07

    申请人： Hyun-Jin Kim ,  Sang-Bo Lee

    发明人： Hyun-Jin Kim ,  Sang-Bo Lee

    IPC分类号： G06F19/00

    CPC分类号： G11C7/22 ,  G11C7/16 ,  G11C7/222

    摘要： A frequency measuring circuit may include an edge detector, a charge pump, and an analog-to-digital (A/D) converter. The edge detector may be configured to generate an output pulse responsive to an edge of an input clock signal. The charge pump may be configured to generate an output signal responsive to the output pulse from the edge detector. The analog-to-digital (A/D) converter may be configured to convert the output signal into a digital value representing a frequency of the input clock signal. Related methods and integrated circuit memory devices are also discussed.

    摘要翻译： 频率测量电路可以包括边缘检测器，电荷泵和模数（A / D）转换器。 边缘检测器可以被配置为响应于输入时钟信号的边缘产生输出脉冲。 电荷泵可以被配置为响应于来自边缘检测器的输出脉冲而产生输出信号。 模拟数字（A / D）转换器可以被配置为将输出信号转换成表示输入时钟信号的频率的数字值。 还讨论了相关方法和集成电路存储器件。

    Methods of generating internal clock signals from external clock signals and of measuring the frequency of external clock signals and related frequency measuring circuits and semiconductor memory devices
    56.
    发明申请
    Methods of generating internal clock signals from external clock signals and of measuring the frequency of external clock signals and related frequency measuring circuits and semiconductor memory devices 失效
    从外部时钟信号产生内部时钟信号以及测量外部时钟信号和相关频率测量电路和半导体存储器件的频率的方法

    公开(公告)号：US20060017429A1

    公开(公告)日：2006-01-26

    申请号：US11184616

    申请日：2005-07-19

    申请人： Hyun-Jin Kim

    发明人： Hyun-Jin Kim

    IPC分类号： G11C27/00

    CPC分类号： G11C7/22 ,  G11C7/222

    摘要： Pursuant to certain embodiments of the present invention, methods of generating an internal clock signal in a semiconductor memory device are provided in which the frequency of an external clock signal is measured. A CAS latency value of the semiconductor memory device is automatically set based at least in part on the measured frequency of the external clock signal. The automatically set CAS latency value is then used to generate the internal clock signal from the external clock signal. In these methods, the delay of a delay lock loop of the semiconductor memory device may be based at least in part on the automatically set CAS latency value. The internal clock signal may be generated from the external clock signal using the delay lock loop. Circuits and methods for measuring the frequency of the external clock signal are also provided.

    摘要翻译： 根据本发明的某些实施例，提供了在半导体存储器件中产生内部时钟信号的方法，其中测量外部时钟信号的频率。 至少部分地基于所测量的外部时钟信号的频率来自动设置半导体存储器件的CAS延迟值。 然后，自动设置CAS延迟值用于从外部时钟信号生成内部时钟信号。 在这些方法中，半导体存储器件的延迟锁定环的延迟可以至少部分地基于自动设置的CAS等待时间值。 可以使用延迟锁定环从外部时钟信号产生内部时钟信号。 还提供了用于测量外部时钟信号频率的电路和方法。

    Polymer for chemically amplified resist and a resist composition using the same
    57.
    发明授权
    Polymer for chemically amplified resist and a resist composition using the same 有权
    用于化学放大抗蚀剂的聚合物和使用其的抗蚀剂组合物

    公开(公告)号：US06767687B1

    公开(公告)日：2004-07-27

    申请号：US10070477

    申请日：2002-07-23

    申请人： Deog-Bae Kim ,  Hyun-Jin Kim ,  Yong-Joon Choi ,  Yoon-Sik Chung

    发明人： Deog-Bae Kim ,  Hyun-Jin Kim ,  Yong-Joon Choi ,  Yoon-Sik Chung

    IPC分类号： G03F7004

    CPC分类号： G03F7/039 ,  G03F7/0045 ,  Y10S430/115

    摘要： The present invention relates to a polymer for a chemically amplified resist and a resist composition using the same. The present invention provides a polymer represented by the Formula (1) and a chemically resist composition for extreme ultraviolet light comprising the same. The chemically amplified resist composition comprising the polymer represented by the formula (1) of the present invention responds to mono wavelength in a micro-lithography process and can embody a micro-pattern of high resolution on a substrate.

    摘要翻译： 本发明涉及一种用于化学放大抗蚀剂的聚合物和使用其的抗蚀剂组合物。 本发明提供由式（1）表示的聚合物和包含该聚合物的用于极紫外光的化学抗蚀剂组合物。 包含本发明的式（1）表示的聚合物的化学放大抗蚀剂组合物在微光刻工艺中响应于单波长，并​​且可以在衬底上体现高分辨率的微图案。