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    PROCESS FOR SELECTIVELY PATTERNING A MAGNETIC FILM STRUCTURE
    51.
    发明申请
    PROCESS FOR SELECTIVELY PATTERNING A MAGNETIC FILM STRUCTURE 失效
    用于选择性地绘制磁性膜结构的方法

    公开(公告)号：US20120115251A1

    公开(公告)日：2012-05-10

    申请号：US13350174

    申请日：2012-01-13

    申请人： David W. Abraham ,  Solomon Assefa ,  Eugene J. O'Sullivan

    发明人： David W. Abraham ,  Solomon Assefa ,  Eugene J. O'Sullivan

    IPC分类号： H01L21/465

    CPC分类号： H01L43/12

    摘要： Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer.

    摘要翻译： 用于选择性地图案化磁性膜结构的方法通常包括通过湿法选择性地蚀刻设置在隧道势垒层上的自由层的暴露部分，其包括将自由层暴露于包含至少一种酸和有机磷酸抑制剂或盐的蚀刻剂溶液 在隧道势垒层上停止。

    Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof
    53.
    发明申请
    Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof 有权
    三维集成电路及其制造技术

    公开(公告)号：US20110133281A1

    公开(公告)日：2011-06-09

    申请号：US13019130

    申请日：2011-02-01

    申请人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    发明人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    IPC分类号： H01L27/12

    CPC分类号： H01L27/0688 ,  H01L25/167 ,  H01L27/144 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

    摘要： Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

    摘要翻译： 提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。 一方面，三维集成电路包括底部器件层和顶部器件层。 底部器件层包括衬底; 与衬底相邻的数字CMOS电路层; 以及与数字CMOS电路层的与衬底相对的一侧相邻的第一结合氧化物层。 顶部器件层包括形成在具有大于或等于约0.5微米厚度的掩埋氧化物（BOX）的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层; 以及与模拟CMOS和光子电路层相邻的第二结合氧化物层。 底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

    Techniques for three-dimensional circuit integration
    54.
    发明授权
    Techniques for three-dimensional circuit integration 有权
    三维电路集成技术

    公开(公告)号：US07955887B2

    公开(公告)日：2011-06-07

    申请号：US12132029

    申请日：2008-06-03

    申请人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    发明人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    IPC分类号： H01L21/20

    CPC分类号： H01L27/0688

    摘要： Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

    摘要翻译： 提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。 一方面，三维集成电路包括底部器件层和顶部器件层。 底部器件层包括数字CMOS电路层; 以及与数字CMOS电路层相邻的第一结合氧化物层。 顶部器件层包括衬底; 形成在与衬底相邻的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层，所述SOI层具有厚度大于或等于约1微米的掩埋氧化物（BOX）; 以及与模拟CMOS和与衬底相对的光子电路层的一侧相邻的第二结合氧化物层。 底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

    Suspended germanium photodetector for silicon waveguide
    55.
    发明授权
    Suspended germanium photodetector for silicon waveguide 有权
    用于硅波导的悬浮锗光电探测器

    公开(公告)号：US07902620B2

    公开(公告)日：2011-03-08

    申请号：US12191687

    申请日：2008-08-14

    申请人： Solomon Assefa ,  Jack O. Chu ,  Martin M. Frank ,  William M. Green ,  Young-hee Kim ,  George G. Totir ,  Joris Van Campenhout ,  Yurii A. Vlasov ,  Ying Zhang

    发明人： Solomon Assefa ,  Jack O. Chu ,  Martin M. Frank ,  William M. Green ,  Young-hee Kim ,  George G. Totir ,  Joris Van Campenhout ,  Yurii A. Vlasov ,  Ying Zhang

    IPC分类号： H01L31/18

    CPC分类号： H01L31/1804 ,  B82Y20/00 ,  G02B6/12004 ,  G02B6/136 ,  G02B2006/12123 ,  H01L31/109 ,  H01L31/1812 ,  Y02E10/547 ,  Y02P70/521

    摘要： A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.

    摘要翻译： 在第一外延硅层的顶表面上外延地形成第一硅锗合金层，第二外延硅层，第二硅锗层和锗层的垂直叠层。 第二外延硅层，第二硅锗层和锗层通过介电盖部分，电介质间隔物和第一硅锗层被图案化和封装。 在第一和第二硅层之间移除硅锗层以形成硅锗台面结构，其结构上支撑包括硅部分，硅锗合金部分，锗光电检测器和介电帽部分的叠层的悬垂结构。 锗光电探测器由硅锗台面结构悬挂而不邻接硅波导。 锗扩散到硅波导和锗检测器中的缺陷密度被最小化。

    Optoelectronic device with germanium photodetector
    56.
    发明授权
    Optoelectronic device with germanium photodetector 有权
    具有锗光电探测器的光电器件

    公开(公告)号：US07790495B2

    公开(公告)日：2010-09-07

    申请号：US11925170

    申请日：2007-10-26

    申请人： Solomon Assefa ,  Stephen Walter Bedell ,  Yurii A. Vlasov ,  Fengnian Xia

    发明人： Solomon Assefa ,  Stephen Walter Bedell ,  Yurii A. Vlasov ,  Fengnian Xia

    IPC分类号： H01L21/00

    CPC分类号： H01L31/1808 ,  G02B6/12004 ,  H01L31/02327 ,  H01L31/105 ,  H01L31/1812 ,  Y02E10/50

    摘要： An optoelectronic device comprises a photodetector feature, an interfacial layer disposed above at least a portion of the photodetector feature, and a vertical contact disposed on at least a portion of the interfacial layer. The photodetector feature comprises germanium and is operative to convert a light signal into an electrical signal. The interfacial layer comprises nickel. Finally, the vertical contact is operative to transmit the electrical signal from the photodetector feature.

    摘要翻译： 光电子器件包括光电检测器特征，设置在光电检测器特征的至少一部分上方的界面层，以及设置在界面层的至少一部分上的垂直接触。 光电检测器特征包括锗并且可操作以将光信号转换成电信号。 界面层包括镍。 最后，垂直接触可操作地从光电检测器特征传输电信号。

    Methods involving resetting spin-torque magnetic random access memory
    60.
    发明授权
    Methods involving resetting spin-torque magnetic random access memory 有权
    涉及复位自旋转矩磁随机存取存储器的方法

    公开(公告)号：US07492631B1

    公开(公告)日：2009-02-17

    申请号：US12118496

    申请日：2008-05-09

    申请人： Solomon Assefa ,  William J. Gallagher ,  Chung H. Lam ,  Jonathan Z. Sun

    发明人： Solomon Assefa ,  William J. Gallagher ,  Chung H. Lam ,  Jonathan Z. Sun

    IPC分类号： G11C11/14

    CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1673

    摘要： An exemplary method for resetting a spin-transfer based random access memory system, the method comprising, inducing a first current through a conductor, wherein the first current is operative to change a direction of orientation of a magnetic reference layer, inducing a second current from the drain terminal to the write terminal via a conductive layer, wherein the second current is operative to change the direction of a magnetic state of a free layer magnet, and inducing a third current through the conductor, wherein the third current is operative to change the direction of magnetic orientation of the reference layer.

    摘要翻译： 一种用于重置基于自旋转移的随机存取存储器系统的示例性方法，所述方法包括：引导通过导体的第一电流，其中所述第一电流可操作以改变磁参考层的取向方向，从而引起来自 所述漏极端子经由导电层到所述写入端子，其中所述第二电流可操作地改变自由层磁体的磁状态的方向，并且引起通过所述导体的第三电流，其中所述第三电流可操作以改变所述第一电流， 参考层的磁性取向方向。