公开(公告)号：US06175252B1

公开(公告)日：2001-01-16

申请号：US09304270

申请日：1999-05-06

申请人： Takashi Yamada

发明人： Takashi Yamada

IPC分类号： H03K190175

CPC分类号： H03K17/167

摘要： There is provided a driver circuit which does not require a large driving current, even when a logic circuit having a large capacity component is connected as the load. When the input voltage level is “H”, the first driving means inserted between the source and the load is maintained at the on state and it is turned off when it is detected by the first detecting means that the voltage level of the load exceeds the first voltage level. When the input voltage level is “L”, the second driving means inserted between the ground and the load is maintained at the on state and it is turned off when it is detected by the second detecting means that the voltage level of the load is below the second voltage level. The above mentioned first voltage level is higher than the logic threshold of the logic gate for receiving signals from the driver circuit, and the above mentioned second voltage level is lower than the logic threshold of the logic gate for receiving signals from the driver circuit.

摘要翻译： 提供了不需要大的驱动电流的驱动电路，即使具有大容量分量的逻辑电路作为负载被连接。当输入电压电平为“H”时，第一驱动装置插入在源和 负载保持在接通状态，并且当第一检测装置检测到负载的电压电平超过第一电压电平时它被关断。 当输入电压电平为“L”时，插入接地和负载之间的第二驱动装置保持在接通状态，并且当第二检测装置检测到负载的电压电平低于 第二电压电平。 上述第一电压电平高于用于从驱动器电路接收信号的逻辑门的逻辑门限，并且上述第二电压电平低于用于从驱动器电路接收信号的逻辑门的逻辑门限。

公开(公告)号：US6147898A

公开(公告)日：2000-11-14

申请号：US263089

申请日：1999-03-08

申请人： Takashi Yamada

发明人： Takashi Yamada

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C11/00

CPC分类号： G11C11/419

摘要： There is disclosed an SRAM including a number of memory cells located in the form of a matrix. When data "0" is written to a memory cell 100, a precharge signal PC is brought to a high level so that a bit line D0 is brought into an electrically floating condition. A corresponding power switch 30 is turned off so that a pseudo-ground line SS0 is brought to an electrically floating condition. A corresponding equalizing transistor 20L is turned on so that the bit line having a power supply voltage Vdd as an initial potential and the pseudo-ground line SS0 having a ground voltage Vss as an initial potential are electrically connected to each other, so that the potential of the pseudo-ground line SS0 is elevated to a potential Veq which is determined by a ratio in capacitance of the bit line and the pseudo-ground line. As a result, the data holding capability of the memory cell 100 is lowered, and therefore, when a corresponding word line is pulled up, a latch in the memory cell 100 is quickly inverted, so that the writing operation is completed at a high speed. After the writing operation, the potential of the bit line D0 is returned to the initial potential Vdd. In this operation, since the potential of the bit line D0 was lowered only to the potential Veq, the potential of the bit line D0 is returned to the initial potential Vdd quickly with a reduced power consumption.

摘要翻译： 公开了包括以矩阵形式定位的多个存储单元的SRAM。 当将数据“0”写入存储单元100时，使预充电信号PC达到高电平，使得位线D0进入电浮动状态。 相应的电源开关30被关闭，使得伪地线SS0变为电浮动状态。 相应的均衡晶体管20L导通，使得具有作为初始电位的电源电压Vdd的位线和具有接地电压Vss作为初始电位的伪地线SS0彼此电连接，使得电位 将伪地线SS0提高到由位线和伪地线的电容比确定的电位Veq。 结果，存储单元100的数据保持能力降低，因此当对应的字线被上拉时，存储单元100中的锁存器被快速反转，使得写入操作以高速完成 。 在写入操作之后，位线D0的电位返回到初始电位Vdd。 在该操作中，由于位线D0的电位仅降低到电位Veq，所以位线D0的电位以降低的功耗快速恢复到初始电位Vdd。

公开(公告)号：US6075397A

公开(公告)日：2000-06-13

申请号：US178829

申请日：1998-10-26

申请人： Takashi Yamada

发明人： Takashi Yamada

IPC分类号： H01L27/04 ,  G11C11/417 ,  G11C11/419 ,  H01L21/822 ,  H03K5/135 ,  H03K17/30 ,  H03L7/06 ,  H03H11/26

CPC分类号： G11C11/419 ,  G11C11/417 ,  H03K5/135

摘要： The present invention provides an technique for compensating a operation speed variation based on a principle that a circuit operation speed is adjusted by reflecting a delay time of an internal circuit itself that is an object of the operation speed fluctuation compensation.An internal circuit (1 in FIG. 1) has a critical path with an output terminal pair that outputs the identical logical values till its each operation is finished, and data in a complementary signal format as soon as its each operation is finished. A logical gate (2 in FIG. 1) can detect its operation end by sensing the signal transition into a complementary signal format at the output terminal pair of the internal circuit.

摘要翻译： 本发明提供了一种基于通过反映作为操作速度波动补偿的对象的内部电路本身的延迟时间来调整电路操作速度的原理来补偿操作速度变化的技术。 内部电路（图1中的1）具有输出端子对的关键路径，其输出相同的逻辑值，直到其每个操作完成，并且一旦其每个操作完成就以互补信号格式的数据。 逻辑门（图1中的2）可以通过感测在内部电路的输出端子对处的信号转换为互补信号格式来检测其操作结束。

公开(公告)号：US6048444A

公开(公告)日：2000-04-11

申请号：US979542

申请日：1997-11-26

申请人： Satoshi Takahashi ,  Hideki Kambara ,  Takashi Yamada

发明人： Satoshi Takahashi ,  Hideki Kambara ,  Takashi Yamada

IPC分类号： G01N27/447 ,  G01N27/26

CPC分类号： G01N27/44782 ,  G01N27/44721

摘要： A capillary electrophoresis apparatus of the invention has: a plurality of capillaries which are filled with a migration medium and have first ends into which samples are injected and second ends in which components included in the samples are eluted; a sheath flow cell in which the second ends are arranged in a straight line at first predetermined intervals and are terminated and a sheath flow is formed; a buffer solution vessel for housing a buffer solution flowing in the sheath flow cell; a drain vessel housing the buffer solution flowed from the sheath flow cell; an optical system emitting laser light to a part near the second ends; and a fluorescent detection system for detecting fluorescent light generated from fluorophore labelling the components included in the sample eluted near the second ends by the emission of laser light, wherein the buffer solution flows from the lower part to the upper part of the sheath flow cell, thereby forming a sheath flow in the sheath flow cell.

摘要翻译： 本发明的毛细管电泳装置具有：填充有迁移介质的多个毛细管，其具有注入样品的第一端和样品中包含的成分被洗脱的第二端; 鞘流池，其中第二端以第一预定间隔以直线布置并且终止并形成鞘流; 用于容纳在鞘流池中流动的缓冲溶液的缓冲溶液容器; 容纳从鞘流池流出的缓冲溶液的排水管; 将激光发射到靠近第二端的部分的光学系统; 以及荧光检测系统，用于检测由荧光团产生的荧光，其中通过发射激光来标记在第二端附近洗脱的样品中包含的成分，其中缓冲溶液从鞘流动池的下部流向上部， 从而在鞘流动池中形成鞘流。

公开(公告)号：US6017765A

公开(公告)日：2000-01-25

申请号：US26720

申请日：1998-02-20

申请人： Takashi Yamada ,  Hideki Kambara

发明人： Takashi Yamada ,  Hideki Kambara

IPC分类号： G01N21/64 ,  G01N27/447 ,  G01N27/26

CPC分类号： G01N27/44721 ,  G01N27/44782

摘要： A fluorescence detection capillary array electrophoresis analyzer comprising a capillary array holder holding a plurality of capillary array units and a transferring unit for transferring in turn the capillary array units held by the capillary array holder to a sample injection station, a fluorescence detection station or a gel refresh station, which reduces the time required for pre-electrophoresis and replacement of a used gel by fresh gel, and conducts efficient and automatic analysis. Furthermore, the analyzer automatically discharges residual samples remaining in the capillaries, and hence automatically analyzes a large number of samples by electrophoresis.

摘要翻译： 一种荧光检测毛细管阵列电泳分析仪，其包括保持多个毛细管阵列单元的毛细管阵列保持器和用于将由毛细管阵列保持器保持的毛细管阵列单元转移到样品注射台，荧光检测站或凝胶的转移单元 刷新站，这减少了预先电泳所需的时间和用新鲜凝胶替代使用的凝胶，并进行有效和自动的分析。 此外，分析仪自动排出残留在毛细管中的残留样品，因此通过电泳自动分析大量样品。

公开(公告)号：US5985427A

公开(公告)日：1999-11-16

申请号：US791100

申请日：1997-01-24

申请人： Toshiaki Ueda ,  Eiji Nakamura ,  Takashi Yamada ,  Takatoshi Oshika

发明人： Toshiaki Ueda ,  Eiji Nakamura ,  Takashi Yamada ,  Takatoshi Oshika

IPC分类号： C23C16/40 ,  C23C30/00 ,  B32B15/04

CPC分类号： C23C30/005 ,  C23C16/403 ,  Y10T428/24975 ,  Y10T428/265

摘要： A coated carbide alloy cutting member is provided exhibiting excellent resistance against chipping, wherein the cutting member has a cemented carbide substrate and one or more hard coating layers including an aluminum oxide-based layer primarily of aluminum oxide, the hard coating layers having an average thickness of 3 to 20 .mu.m and being formed on the cemented carbide substrate by chemical and/or physical vapor deposition; and wherein the aluminum oxide-based layer contains 0.005 to 0.5 percent by weight of chlorine.

摘要翻译： 提供了具有优异的抗切削性的涂层碳化物合金切割构件，其中切割构件具有硬质合金基底和一个或多个包括主要由氧化铝形成的氧化铝基层的硬涂层，硬涂层具有平均厚度 通过化学和/或物理气相沉积在硬质合金基底上形成3至20μm; 并且其中所述氧化铝基层含有0.005至0.5重量％的氯。

公开(公告)号：US5968331A

公开(公告)日：1999-10-19

申请号：US554808

申请日：1995-11-07

申请人： Hideki Kambara ,  Satoshi Takahashi ,  Takashi Anazawa ,  Takashi Yamada

发明人： Hideki Kambara ,  Satoshi Takahashi ,  Takashi Anazawa ,  Takashi Yamada

IPC分类号： G01N33/50 ,  G01N27/447 ,  G01N27/26

CPC分类号： G01N27/44743

摘要： A sample holding device for electrophoresis apparatus according to the present invention wherein a plurality of sample holding capillaries are laid out in an array and are immobilized to the supporting jig. This sample holding device is configured to ensure the lower ends of the capillaries can contact the sample injection portion of the electrophoresis separation part of the electrophoresis apparatus, and provides easy sample injection and prevents the gel capillaries of the electrophoresis separation part from being damaged when sample holding capillaries are filled with gels, thereby allowing repeated use of the gel capillaries of the electrophoresis separation part.

摘要翻译： 根据本发明的用于电泳装置的样品保持装置，其中多个样品保持毛细管以阵列布置并固定在支撑夹具上。 该样品保持装置被配置为确保毛细血管的下端可以接触电泳装置的电泳分离部的样品注入部，并且提供容易的样品注射，并且防止当样品时电泳分离部分的凝胶毛细血管损伤 保持毛细血管填充凝胶，从而允许重复使用电泳分离部分的凝胶毛细血管。

公开(公告)号：US5912591A

公开(公告)日：1999-06-15

申请号：US24298

申请日：1998-02-17

申请人： Takashi Yamada

发明人： Takashi Yamada

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/786 ,  H03K3/0231 ,  H03K3/03 ,  H03K3/354 ,  H03B5/24

CPC分类号： H03K3/354 ,  H03K3/0231 ,  H03K3/03 ,  H03K3/0322 ,  H03K2217/0018

摘要： The present invention provides a novel circuitry comprising a series connection of a plurality of invertor gates, each of which has field effect transistors, wherein at least one of the field effect transistors has a back bias control terminal; and a various bias voltage generator being capable of generating at least one bias voltage and also capable of varying the at least one bias voltage individually, the various bias voltage generator being also electrically connected to the back bias control terminal of the at least one of the field effect transistors for applying the at least one bias voltage to the back bias control terminal so that the various bias voltage generator is operated to individually vary the at least one bias voltage thereby to individually vary a threshold voltage of the at least one of the field effect transistors.

摘要翻译： 本发明提供了一种新颖的电路，其包括多个反相器门的串联连接，每个反相器门均具有场效应晶体管，其中至少一个场效应晶体管具有背偏置控制端; 以及各种偏置电压发生器，其能够产生至少一个偏置电压并且还能够单独地改变所述至少一个偏置电压，所述各种偏置电压发生器还电连接到所述至少一个偏置电压的反偏压控制端子 用于将至少一个偏置电压施加到背偏压控制端子的场效应晶体管，使得各种偏置电压发生器被操作以单独地改变至少一个偏置电压，从而单独地改变场中的至少一个的阈值电压 效应晶体管。

公开(公告)号：US5868854A

公开(公告)日：1999-02-09

申请号：US987171

申请日：1992-12-08

申请人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

发明人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

IPC分类号： C23F4/00 ,  H01J37/18 ,  H01L21/00 ,  H01L21/3213 ,  H01L21/461 ,  H01L21/677 ,  B08B6/00 ,  H01L21/302

CPC分类号： H01L21/32136 ,  C23F4/00 ,  H01J37/185 ,  H01L21/67017 ,  H01L21/67028 ,  H01L21/67069 ,  H01L21/67161 ,  H01L21/67207 ,  H01L21/67745 ,  H01L21/67751

摘要： Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

公开(公告)号：US5635312A

公开(公告)日：1997-06-03

申请号：US571134

申请日：1995-12-12

申请人： Shuichi Yanagisawa ,  Takashi Yamada ,  Taishi Tsuji ,  Fumio Matsui

发明人： Shuichi Yanagisawa ,  Takashi Yamada ,  Taishi Tsuji ,  Fumio Matsui

IPC分类号： H01M4/64 ,  H01M4/66 ,  H01M6/10 ,  H01M6/16 ,  H01M10/04 ,  H01M10/05 ,  H01M10/0583 ,  H01M4/00

CPC分类号： H01M6/10 ,  H01M10/0436 ,  H01M4/661 ,  H01M6/16

摘要： There is provided a layer-built chemical cell device, comprising a positive electrode including a current collecting material and an active substance, a negative electrode including another current collecting material and another active substance, an electrolyte and a separator both interposed between the positive electrode and the negative electrode. In such a layer-built cell device, the positive electrode and the negative electrode are in a belt-like shape, and are folded upon each other in a manner such that one electrode is always faced on both sides thereof with the other electrode, so as to form an electrode pair.

摘要翻译： 提供了一种层状化学电池器件，其包括包含集电材料和活性物质的正电极，包括另外的集电材料的负电极和另外的活性物质，电解质和隔膜，两者都介于正电极和 负极。 在这种层状电池装置中，正极和负极呈带状，并且以使得一个电极总是与另一个电极面对的方式彼此折叠，因此 以形成电极对。