公开(公告)号：US20130251144A1

公开(公告)日：2013-09-26

申请号：US13990829

申请日：2011-10-24

申请人： Harunaga Hiwatari ,  Toru Akishita

发明人： Harunaga Hiwatari ,  Toru Akishita

IPC分类号： H04L9/28

CPC分类号： H04L9/28 ,  G09C1/00 ,  H04L9/0625 ,  H04L2209/122

摘要： A reduction in the size of encryption processing configuration applying generalized Feistel structures is achieved. The encryption processing configuration applies a generalized Feistel structure for dividing and inputting data into multiple lines, and repeatedly executing data transformation processing applying a round function on the data transferred to each line, and during the execution cycle of a matrix operation by a matrix operation executing unit for executing linear transformation processing applying a matrix on the data in a first line, an operation is executed on the matrix operation processing data from the initial cycle and data in a second line. This configuration enables a register to be used for both the storage of the data for the second line and the storage of the results of the matrix operation on the first line of data in progress, a reduction in the total number of registers, and thus a reduction in size.

摘要翻译： 实现了使用广义Feistel结构的加密处理配置的大小的减小。 加密处理配置应用广义的Feistel结构，用于将数据分割和输入到多行，并且重复执行对传送到每行的数据应用循环函数的数据变换处理，并且在矩阵运算的执行周期期间通过执行矩阵运算 用于执行对第一行中的数据应用矩阵的线性变换处理的单元，对来自初始周期的矩阵运算处理数据和第二行中的数据执行运算。 该配置使得寄存器能够用于存储第二行的数据以及在正在进行的第一行数据上存储矩阵运算的结果，总共减少寄存器的数量 尺寸减小

公开(公告)号：US20130244062A1

公开(公告)日：2013-09-19

申请号：US13988162

申请日：2011-03-11

申请人： Shigeki Teramoto ,  Shinichi Uesaka ,  Atsushi Ozawa ,  Kazuo Nakamura ,  Asami Yoshida ,  Toru Akishita ,  Shiho Moriai

发明人： Shigeki Teramoto ,  Shinichi Uesaka ,  Atsushi Ozawa ,  Kazuo Nakamura ,  Asami Yoshida ,  Toru Akishita ,  Shiho Moriai

IPC分类号： H01M10/42

CPC分类号： H01M10/4257 ,  H01M10/0431 ,  H01M10/4207 ,  H01M10/425 ,  H01M10/48 ,  H01M10/482 ,  H01M2010/4278

摘要： Provided is a secondary battery cell that can certainly prevent detachment of an integrated circuit from the secondary battery cell and attachment of the integrated circuit to another secondary battery cell, a battery pack including such secondary battery cells, and an electric power consumption device including such a battery pack.A secondary battery cell 20 of the present invention includes an integrated circuit (an IC chip) 50 that has stored identification information, and the integrated circuit 50 is driven by power from the secondary battery cell. A battery pack of the present invention includes secondary battery cells each including an integrated circuit (an IC chip) that has stored identification information, and the integrated circuits are driven by power from the secondary battery cells. An electric power consumption device of the present invention contains a battery pack that includes secondary battery cells each including an integrated circuit (an IC chip) that has stored identification information, and the integrated circuits are driven by power from the secondary battery cells.

摘要翻译： 本发明提供二次电池单元，其可以防止集成电路从二次电池单元的脱离和集成电路与另一二次电池单元的连接，包括这种二次电池单元的电池组以及包括这种二次电池的电力消耗装置 电池组。 本发明的二次电池单元20包括具有存储识别信息的集成电路（IC芯片）50，并且集成电路50由来自二次电池单元的电力驱动。 本发明的电池组包括二次电池单元，每个二次电池单元包括具有存储的识别信息的集成电路（IC芯片），并且集成电路由来自二次电池单元的电力驱动。 本发明的电力消耗装置包含电池组，其包括二次电池单元，二次电池单元具有存储了识别信息的集成电路（IC芯片），并且集成电路由来自二次电池单元的电力驱动。

公开(公告)号：US20070291937A1

公开(公告)日：2007-12-20

申请号：US11791283

申请日：2005-11-15

申请人： Masanobu Katagi ,  Toru Akishita ,  Izuru Kitamura ,  Tsuyoshi Takagi

发明人： Masanobu Katagi ,  Toru Akishita ,  Izuru Kitamura ,  Tsuyoshi Takagi

IPC分类号： H04L9/30

CPC分类号： G06F7/725 ,  G06F2207/7261

摘要： An apparatus and a method for performing a hyperelliptic curve cryptography process at a high speed in a highly secure manner are provided. A base point D is produced such that the base point D and one or more of precalculated data in addition to the base point used in a scalar multiplication operation based on a window algorithm are degenerate divisors with a weight smaller than genus g of a hyperelliptic curve. An addition operation included in the scalar multiplication operation based on the window algorithm is accomplished by performing an addition operation of adding a degenerate divisor and a non-degenerate divisor, whereby a high-speed operation is achieved without causing degradation in security against key analysis attacks such as SPA.

摘要翻译： 提供了一种以高度安全的方式高速执行超椭圆曲线密码处理的装置和方法。 产生基点D，使得除了基于窗口算法的标量乘法运算中使用的基点之外，基点D和预先计算的数据中的一个或多个是具有小于超椭圆曲线的g的权重的简并因数 。 基于窗口算法的标量乘法运算中包含的加法运算通过执行加法简并因子和非简并因数的加法运算来实现，从而实现高速运算，而不会导致安全性降低密钥分析攻击 如SPA。

公开(公告)号：US09031230B2

公开(公告)日：2015-05-12

申请号：US13990829

申请日：2011-10-24

申请人： Harunaga Hiwatari ,  Toru Akishita

发明人： Harunaga Hiwatari ,  Toru Akishita

IPC分类号： H04L9/00 ,  H04L9/28 ,  H04L9/06

CPC分类号： H04L9/28 ,  G09C1/00 ,  H04L9/0625 ,  H04L2209/122

摘要： A reduction in the size of encryption processing configuration applying generalized Feistel structures is achieved. The encryption processing configuration applies a generalized Feistel structure for dividing and inputting data into multiple lines, and repeatedly executing data transformation processing applying a round function on the data transferred to each line, and during the execution cycle of a matrix operation by a matrix operation executing unit for executing linear transformation processing applying a matrix on the data in a first line, an operation is executed on the matrix operation processing data from the initial cycle and data in a second line. This configuration enables a register to be used for both the storage of the data for the second line and the storage of the results of the matrix operation on the first line of data in progress, a reduction in the total number of registers, and thus a reduction in size.

摘要翻译： 实现了使用广义Feistel结构的加密处理配置的大小的减小。 加密处理配置应用广义的Feistel结构，用于将数据分割和输入到多行，并且重复执行对传送到每行的数据应用循环函数的数据变换处理，并且在矩阵运算的执行周期期间通过执行矩阵运算 用于执行对第一行中的数据应用矩阵的线性变换处理的单元，对来自初始周期的矩阵运算处理数据和第二行中的数据执行运算。 该配置使得寄存器能够用于存储第二行的数据以及在正在进行的第一行数据上存储矩阵运算的结果，总共减少寄存器的数量 尺寸减小

公开(公告)号：US20100183142A1

公开(公告)日：2010-07-22

申请号：US12087811

申请日：2007-01-04

申请人： Masanobu Katagi ,  Izuru Kitamura ,  Toru Akishita

发明人： Masanobu Katagi ,  Izuru Kitamura ,  Toru Akishita

IPC分类号： H04L9/28

CPC分类号： H04L9/003 ,  G06F7/725 ,  H04L9/3066 ,  H04L2209/08

摘要： An apparatus and method for performing a high-speed operation in a hyperelliptic curve cryptography process are provided. If a standard divisor having a weight equal to a genus g in the hyperelliptic curve cryptography of genus g is a target divisor of scalar multiplication, a determination as to whether the standard divisor is divisible into a theta divisor defined as a divisor having a weight less than the genus g is determined, and if the standard divisor is divisible, the theta divisor is generated by dividing the standard divisor, and a scalar multiplication executing block performs the scalar multiplication using the theta divisor. With this arrangement, the scalar multiplication is performed at high speed with an amount of calculation reduced, and a high-speed encryption processing operation is thus performed.

摘要翻译： 提供了一种用于在超椭圆曲线加密处理中执行高速操作的装置和方法。 如果具有与g类的超椭圆曲线密码学中的g类重量相等的标准因子是标量乘法的目标除数，则确定标准因数是否可被除以被定义为具有权重较小的除数的因数因子 确定g，并且如果标准因数是可除的，则通过划分标准因数来产生θ因数，并且标量乘法执行块使用θ因数执行标量乘法。 利用这种布置，减少了计算量，高速执行标量乘法，从而执行高速加密处理操作。

公开(公告)号：US07697683B2

公开(公告)日：2010-04-13

申请号：US11065941

申请日：2005-02-25

申请人： Masanobu Katagi ,  Toru Akishita ,  Izuru Kitamura ,  Tsuyoshi Takagi

发明人： Masanobu Katagi ,  Toru Akishita ,  Izuru Kitamura ,  Tsuyoshi Takagi

IPC分类号： H04L9/28 ,  H04L9/14

CPC分类号： G06F7/725 ,  H04L9/3066

摘要： A cryptography-processing method for carrying out computation processing of hyperelliptic curve cryptography at a high speed and a cryptography-processing apparatus for implementing the method. In execution of scalar multiplication processing, a divisor is selected among divisors each having a weight g.sub.0 smaller than the genus g of a hyperelliptic curve where 1≦.g0.

摘要翻译： 一种用于高速执行超椭圆曲线密码术的计算处理的密码处理方法和用于实现该方法的密码处理装置。 在执行标量乘法处理时，选择除数之间的除数，它们的权重小于超椭圆曲线g的权重，其中1＆nlE; .g0。

公开(公告)号：US07659837B2

公开(公告)日：2010-02-09

申请号：US11948582

申请日：2007-11-30

申请人： Yoshikazu Miyato ,  Toru Akishita

发明人： Yoshikazu Miyato ,  Toru Akishita

IPC分类号： H03M7/00

CPC分类号： H03M5/04 ,  H04L9/003 ,  H04L9/0618 ,  H04L2209/12

摘要： An operation processing apparatus adapted to perform a data conversion on input bits has a logic circuit adapted to perform a data conversion on input bits. The logic circuit includes selectors configured in a hierarchical layer structure and controlled by select signals corresponding to the input bits. Constant values input to selectors located in a bottom layer of the hierarchical structure are selected and transferred toward a top layer from one layer to another. A constant value is finally selected and output from the top layer. The data conversion process is controlled by a control unit such that a pre-charge phase and an evaluation phase are performed alternately. In the pre-charge phase, all input values to the selectors are set to be equal. In the evaluation phase, an output bit for given input bits is produced. The select signals are switched in the pre-charge phase.

摘要翻译： 适于对输入比特执行数据转换的操作处理装置具有适于对输入比特执行数据转换的逻辑电路。 逻辑电路包括以分级层结构配置并由对应于输入位的选择信号控制的选择器。 选择输入到位于分层结构底层的选择器的常数值，并将其从顶层转移到另一层。 最后选择一个恒定值并从顶层输出。 数据转换处理由控制单元控制，使得交替执行预充电阶段和评估阶段。 在预充电阶段，选择器的所有输入值都被设置为相等。 在评估阶段，产生给定输入位的输出位。 选择信号在预充电阶段切换。

公开(公告)号：US20070211894A1

公开(公告)日：2007-09-13

申请号：US11653182

申请日：2007-01-12

申请人： Toru Akishita ,  Masanobu Katagi

发明人： Toru Akishita ,  Masanobu Katagi

IPC分类号： H04L9/30

CPC分类号： G06F7/725 ,  G06F7/4824 ,  G06F2207/7261

摘要： An encryption processing apparatus for performing a scalar multiplication of kP+lQ based on two points P and Q on an elliptic curve and scalar values k and l or a scalar multiplication of kD1+lD2 based on divisors D1 and D2 and scalar values k and l may include a scalar value controller configured to generate joint regular form of (k, l), k= and l= , which are set so that all the bits of the scalar values k and l are represented by 0, +1, or −1, and the combination (ki, li) of bits at positions corresponding to the scalar values k and l is set to satisfy (ki, li)=(0, ±1) or (±1, 0); and a computation execution section configured to perform a process for computing a scalar multiplication of kP+lQ or kD1+lD2.

摘要翻译： 一种加密处理装置，用于基于椭圆曲线上的两个点P和Q执行kP + 1Q的标量乘法，并且标量值k和l或kD1 + 1D2的标量乘法 标量值k和l可以包括标量值控制器，其被配置为产生（k，l）的联合规则形式， ，k =＆lt; K＆lt; n＆gt; 。 。 k <0 和l = 将与标量值k和l相对应的位置的位设置为满足（k i，i，i，i） （0，±1）或（±1，0）; 以及计算执行部，被配置为执行用于计算kP + 1Q或kD1 + 1D2×2的标量乘法的处理。

公开(公告)号：US20050201553A1

公开(公告)日：2005-09-15

申请号：US11065941

申请日：2005-02-25

申请人： Masanobu Katagi ,  Toru Akishita ,  Izuru Kitamura ,  Tsuyoshi Takagi

发明人： Masanobu Katagi ,  Toru Akishita ,  Izuru Kitamura ,  Tsuyoshi Takagi

IPC分类号： G09C1/00 ,  G06F7/72 ,  H04L9/30 ,  H04K1/00 ,  H04L9/00

CPC分类号： G06F7/725 ,  H04L9/3066

摘要： The present invention provides a cryptography-processing method for carrying out computation processing of hyperelliptic curve cryptography processing at a high speed and a cryptography-processing apparatus for implementing the method. In execution of scalar multiplication processing, a divisor is selected among divisors each having a weight g0 smaller than the genus g of a hyperelliptic curve where 1≦g0

摘要翻译： 本发明提供一种用于执行高速超椭圆曲线密码处理的计算处理的密码处理方法和用于实现该方法的密码处理装置。 在执行标量乘法处理中，除数除以上，除数除以小于等于超椭圆曲线g的权重g <0>的除数之外，其中1≤G≤0< 作为基点。 在该配置中对于2的类别进行的超椭圆曲线密码术中，标量乘法的计算处理可以从HarleyADD改变为执行步骤为ExHarADD <2> 1-> 2 ，其中少量 计算处理步骤。 另一方面，对于类别g，标量乘法的计算处理可以从HarleyADD改变为执行步骤ExHarADD 3+ 2-> 3或ExHarADD 3+ 1- > 3 ，具有少量的计算处理步骤。 通过如上所述改变计算处理，可以提高处理速度。