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96 条记录 (耗时 0.024 秒)

    Forming a trench mask comprising a DLC and ASH protecting layer
    51.
    发明授权
    Forming a trench mask comprising a DLC and ASH protecting layer 有权
    形成包括DLC和ASH保护层的沟槽掩模

    公开(公告)号：US06316329B1

    公开(公告)日：2001-11-13

    申请号：US09473121

    申请日：1999-12-28

    申请人： Toshiyuki Hirota ,  Shinji Nakagawa

    发明人： Toshiyuki Hirota ,  Shinji Nakagawa

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224 ,  Y10S438/952

    摘要： In a process for fabricating a semiconductor device, an DLC (diamond like carbon) film is formed on a principal surface of a semiconductor substrate, and an ashing protecting film is formed on the DLC film for protecting the DLC film from an ashing. A hard mask film having a resisting property against an etching agent for the ashing protecting film and the DLC film, is formed on the ashing protecting film. The hard mask film is patterned using a patterned photo resist film as a mask, and then, the patterned photo resist film is removed by an oxygen ashing. The ashing protecting film and the DLC film is patterned using the patterned hard mask film as a mask, and a trench is formed in the principal surface of the semiconductor substrate using the patterned hard mask film, ashing protecting film and DLC film as a mask. An insulator film is deposited on the whole surface to completely fill up the trench. The deposited insulator film, the hard mask film and the ashing protecting film are etched back by a chemical mechanical polishing, using the DLC film as an etching stopper. The DLC film is removed by the ashing, so that the deposited insulator film remains in only the trench to constitute a trench isolation structure.

    摘要翻译： 在制造半导体器件的方法中，在半导体衬底的主表面上形成DLC（类金刚石碳）膜，并且在DLC膜上形成灰化保护膜以保护DLC膜免受灰化。 在灰化保护膜上形成有对抗灰化保护膜和DLC膜的蚀刻剂具有抵抗性的硬掩模膜。 使用图案化的光致抗蚀剂膜作为掩模对硬掩模膜进行图案化，然后通过氧灰化除去图案化的光刻胶膜。 使用图案化的硬掩模膜作为掩模对灰化保护膜和DLC膜进行图案化，并且使用图案化的硬掩模膜，灰化保护膜和DLC膜作为掩模在半导体衬底的主表面中形成沟槽。 绝缘膜沉积在整个表面上以完全填满沟槽。 通过化学机械抛光将沉积的绝缘膜，硬掩模膜和灰化保护膜回蚀刻，使用DLC膜作为蚀刻停止层。 通过灰化除去DLC膜，使得沉积的绝缘体膜仅保留在沟槽中以构成沟槽隔离结构。

    Method for manufacturing semiconductor device
    52.
    发明授权
    Method for manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US6046082A

    公开(公告)日：2000-04-04

    申请号：US89541

    申请日：1998-06-03

    申请人： Toshiyuki Hirota

    发明人： Toshiyuki Hirota

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L28/84

    摘要： According to the present invention, there is provided a means which can prevent a formation failure of hemispherical silicon crystal grains of DRAM having a stacked capacitor structure having the hemispherical silicon crystal grains, can introduce a sufficient amount of an impurity into the hemispherical silicon crystal grains, and can prevent capacity deterioration by depletion. In the present invention, a first silicon film is formed on a semiconductor substrate incorporated with an MOS transistor and then worked into a predetermined shape, and a spontaneous oxide layer is then formed on the surface of the first silicon film. In succession, a second silicon film containing the impurity and a third silicon film containing no impurity are formed, and annealing is then done without exposing it to the atmosphere to form the hemispherical silicon crystal grains. Afterward, electrodes are separated from each other by etch back to form storage electrodes, and a dielectric film and a plate electrode are formed to prepare a capacitor.

    摘要翻译： 根据本发明，提供了一种能够防止具有具有半球形硅晶粒的层叠电容器结构的DRAM的半球状硅晶粒的形成失效的手段，能够将足够量的杂质引入半球状硅晶粒 ，并且可以防止由于耗尽而导致的容量恶化。 在本发明中，在包含MOS晶体管的半导体衬底上形成第一硅膜，然后加工成预定的形状，然后在第一硅膜的表面上形成自发氧化层。 接着，形成含有杂质的第二硅膜和不含杂质的第三硅膜，然后进行退火而不暴露于大气中以形成半球形硅晶粒。 然后，通过蚀刻将电极彼此分离以形成存储电极，并且形成电介质膜和平板电极以制备电容器。

    Process of fabricating miniature memory cell having storage capacitor with wide surface area
    53.
    发明授权
    Process of fabricating miniature memory cell having storage capacitor with wide surface area 失效
    制造具有宽表面积的储能电容器的微型存储单元的工艺

    公开(公告)号：US5926709A

    公开(公告)日：1999-07-20

    申请号：US621954

    申请日：1996-03-26

    申请人： Fumiki Aisou ,  Toshiyuki Hirota

    发明人： Fumiki Aisou ,  Toshiyuki Hirota

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852

    摘要： A node contact hole is formed in an inter-level insulating layer through an anisotropic etching using an inner conductive side wall formed in a primary opening as an etching mask, and an outer conductive side wall concurrently formed from a doped polysilicon together with a conductive plug in the node contact hole increases the surface area of a storage node electrode of a stacked storage capacitor.

    摘要翻译： 通过使用形成在初级开口中的内导电侧壁作为蚀刻掩模，通过各向异性蚀刻在层间绝缘层中形成节点接触孔，以及由掺杂多晶硅与导电插塞同时形成的外导电侧壁 在节点接触孔中增加层叠存储电容器的存储节点电极的表面积。

    Inexpensive electrode materials to facilitate rutile phase titanium oxide
    59.
    发明授权
    Inexpensive electrode materials to facilitate rutile phase titanium oxide 有权
    廉价的电极材料，以促进金红石相氧化钛

    公开(公告)号：US08318572B1

    公开(公告)日：2012-11-27

    申请号：US12708872

    申请日：2010-02-19

    申请人： Sunil Shanker ,  Xiangxin Rui ,  Pragati Kumar ,  Hanhong Chen ,  Toshiyuki Hirota

    发明人： Sunil Shanker ,  Xiangxin Rui ,  Pragati Kumar ,  Hanhong Chen ,  Toshiyuki Hirota

    IPC分类号： H01L21/20 ,  H01L21/8242 ,  H01L21/8234 ,  H01L21/8244 ,  H01L21/3205

    CPC分类号： H01L28/60 ,  C23C16/405 ,  H01L27/10852 ,  H01L28/40

    摘要： This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

    摘要翻译： 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，底部电极具有选择用于晶格匹配特性的材料。 该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度 以较低的成本。

    Semiconductor device, method of manufacturing the same and adsorption site blocking atomic layer deposition method
    60.
    发明授权
    Semiconductor device, method of manufacturing the same and adsorption site blocking atomic layer deposition method 失效
    半导体器件及其制造方法和吸附点阻挡原子层沉积法

    公开(公告)号：US08288241B2

    公开(公告)日：2012-10-16

    申请号：US13245515

    申请日：2011-09-26

    申请人： Toshiyuki Hirota ,  Takakazu Kiyomura ,  Yuichiro Morozumi ,  Shingo Hishiya

    发明人： Toshiyuki Hirota ,  Takakazu Kiyomura ,  Yuichiro Morozumi ,  Shingo Hishiya

    IPC分类号： H01L21/02

    CPC分类号： H01L28/40 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/0228

    摘要： To provide a dielectric film having good crystallinity while suppressing an influence of the size effects and preventing the dielectric film from being divided by an Al-doped layer although there is provided the Al-doped layer for improving the leakage characteristics in the dielectric film of a capacitor, the dielectric film has at least one Al-doped layer, and an area density of Al atoms in one layer of the Al-doped layer is smaller than 1.4E+14 atoms/cm2. Further, to achieve the area density, there is employed a combination of formation of a dielectric film using a general ALD method and Al doping using an adsorption site blocking ALD method including adsorbing a blocker molecule restricting an adsorption site of an Al source, adsorbing the Al source, and introducing a reaction gas for reaction.

    摘要翻译： 为了提供具有良好结晶性的电介质膜，同时抑制尺寸效应的影响并且防止电介质膜被Al掺杂层划分，尽管提供了用于改善电介质膜中的泄漏特性的Al掺杂层 电介质膜具有至少一个Al掺杂层，并且Al掺杂层的一层中的Al原子的面密度小于1.4E + 14原子/ cm 2。 此外，为了实现面积密度，采用通常的ALD法形成电介质膜和使用吸附位阻挡ALD法的Al掺杂的组合，其包括吸附限制Al源的吸附位点的阻断分子，吸附 Al源，并引入反应气体进行反应。