公开(公告)号：US08525092B2

公开(公告)日：2013-09-03

申请号：US13018949

申请日：2011-02-01

申请人： Yoshio Hagihara

发明人： Yoshio Hagihara

IPC分类号： H01L27/00 ,  H03M1/12

CPC分类号： H01L27/146 ,  H03K21/00

摘要： A data processing method may include counting one of a plurality of clock signals with a first mode, counting clock signals based on a predetermined number of the plurality of clock signals with the first mode, to output a first clock signal every time a counter value becomes a first predetermined value, counting the first clock signal with the first mode, counting one of the clock signals with a second mode while the counted value is considered as a first initial value, counting clock signals based on the predetermined number of the plurality of clock signals with the second mode, to output a second clock signal every time the counter value becomes a second predetermined value while the counted value is considered as a second initial value, counting the second clock signal with the second mode, and outputting the counter values with the second mode as difference data between a first data signal and a second data signal.

摘要翻译： 数据处理方法可以包括以第一模式计数多个时钟信号中的一个，基于具有第一模式的多个时钟信号的预定数量对时钟信号进行计数，以在每当计数器值变为 第一预定值，以第一模式对第一时钟信号进行计数，以第二模式计数一个时钟信号，同时将该计数值视为第一初始值，基于多个时钟的预定数量对时钟信号进行计数 信号与第二模式，以在每当计数器值变为第二预定值时输出第二时钟信号，同时将该计数值视为第二初始值，以第二模式对第二时钟信号进行计数，并且用 第二模式作为第一数据信号和第二数据信号之间的差分数据。

公开(公告)号：US08476570B2

公开(公告)日：2013-07-02

申请号：US13285545

申请日：2011-10-31

申请人： Yoshio Hagihara

发明人： Yoshio Hagihara

IPC分类号： H01L27/00

CPC分类号： H04N5/378 ,  H04N5/3577

摘要： A solid-state image pickup device may include: an image pickup unit in which a plurality of pixels are arranged in a matrix; a sample-and-hold unit having a switch element and a capacitance element; a frequency conversion unit in which a plurality of stages of inverting circuits are connected, the pixel signal is supplied to the first power supply terminal, and a start signal for starting clock generation and an output signal from the inverting circuit of a predetermined stage are input to one of the inverting circuits; a counting unit that counts the clock output from the frequency conversion unit; and a buffer circuit provided between a first terminal of the capacitance element connected to the switch element and the first power supply terminal, wherein a second terminal of the capacitance element is connected to the second power supply terminal.

摘要翻译： 固态图像拾取装置可以包括：其中多个像素被布置成矩阵的图像拾取单元; 具有开关元件和电容元件的采样保持单元; 一个频率转换单元，其中连接有多级反相电路，将像素信号提供给第一电源端，并且输入用于开始时钟产生的起始信号和来自预定级的反相电路的输出信号 到一个反相电路; 计数单元，对来自变频单元的时钟输出进行计数; 以及缓冲电路，设置在与开关元件连接的电容元件的第一端子与第一电源端子之间，其中电容元件的第二端子连接到第二电源端子。

公开(公告)号：US20130063295A1

公开(公告)日：2013-03-14

申请号：US13610062

申请日：2012-09-11

申请人： Yoshio Hagihara

发明人： Yoshio Hagihara

IPC分类号： H03M1/56 ,  H01L27/146

CPC分类号： H03M1/145 ,  H03M1/123 ,  H03M1/56 ,  H04N5/378

摘要： In an A/D conversion circuit and an imaging device, an upper counter acquires a first upper count value by performing counting using one output signal, which constitutes a first lower phase signal output from a delay circuit, as a count clock. After values of bits constituting the first upper count value are inverted, the upper counter acquires a second upper count value by performing counting using one output signal, which constitutes a second lower phase signal output from the delay circuit, as a count clock, and further performing counting based on an upper count clock output from a lower counter. A modification unit modifies a logic state of a count clock to a predetermined state when the count clock of the upper counter is switched.

摘要翻译： 在A / D转换电路和成像装置中，上计数器通过使用构成从延迟电路输出的第一下相位信号的一个输出信号作为计数时钟进行计数来获取第一上计数值。 在构成第一上计数值的位的值被反转之后，上计数器通过使用构成从延迟电路输出的第二较低相位信号的一个输出信号作为计数时钟进行计数来获取第二上计数值，并且进一步 基于从下计数器输出的上计数时钟进行计数。 当切换上位计数器的计数时钟时，修改单元将计数时钟的逻辑状态修改为预定状态。

公开(公告)号：US08310390B2

公开(公告)日：2012-11-13

申请号：US12994604

申请日：2009-05-22

申请人： Yoshio Hagihara

发明人： Yoshio Hagihara

IPC分类号： H03M1/50

CPC分类号： H04N5/378 ,  H03K3/0315 ,  H03K5/1504 ,  H03M1/14 ,  H03M1/502 ,  H03M1/60 ,  H04N5/3765

摘要： A clock generating circuit in which a plurality of stages of inverting circuits are connected, a start signal that causes start of clock generation and an output signal from the inverting circuit of a predetermined stage are input to one of the inverting circuits, an element having impedance that changes in accordance with a magnitude of an object analog signal that is an object of conversion to a digital signal is provided between the adjacent inverting circuits, generates a clock of a frequency in accordance with the magnitude of the object analog signal. A counter counts the number of clocks generated by the clock generating circuit and outputs a count value.

摘要翻译： 一个时钟发生电路，其中连接有多级反相电路，将启动时钟产生的起始信号和来自预定级的反相电路的输出信号输入到反相电路中的一个，具有阻抗的元件 在相邻的反相电路之间设置根据作为数字信号的转换对象的目标模拟信号的幅度的变化，根据对象模拟信号的大小产生频率的时钟。 计数器对由时钟发生电路产生的时钟数进行计数，并输出计数值。

公开(公告)号：US20120229666A1

公开(公告)日：2012-09-13

申请号：US13413773

申请日：2012-03-07

申请人： Yoshio Hagihara

发明人： Yoshio Hagihara

IPC分类号： H04N5/228 ,  H03M1/60

CPC分类号： H04N5/378

摘要： An A/D conversion circuit includes a reference signal generation unit, a comparison unit, a delay circuit, a latch unit, an arithmetic circuit, a lower counter, and an upper counter including a second binary counter performing counting using the count clock based on one of the output signals constituting the first lower phase signal, performs counting to acquire a first upper count value, inverts values of respective bits constituting the first upper count value, performs counting using the count clock based on of the output signals constituting the second lower phase signal, and performs counting based on the second upper count clock to acquire a second upper count value, and having a data protection function for protecting an upper count value held by the second binary counter at a time of count clock switching, wherein digital data corresponding to a difference between the first and second analog signals is acquired.

摘要翻译： A / D转换电路包括参考信号产生单元，比较单元，延迟电路，锁存单元，运算电路，下计数器和上计数器，该计数器包括使用计数时钟进行计数的第二二进制计数器 构成第一下相位信号的输出信号中的一个执行计数以获取第一上计数值，对构成第一上计数值的各位的值进行反转，基于构成第二较低计数值的输出信号，使用计数时钟进行计数 并且基于第二上计数时钟执行计数以获取第二上计数值，并且具有用于在计数时钟切换时保护由第二二进制计数器保持的上计数值的数据保护功能，其中数字数据 对应于第一和第二模拟信号之间的差异被获取。

公开(公告)号：US20120194716A1

公开(公告)日：2012-08-02

申请号：US13357031

申请日：2012-01-24

申请人： Yoshio Hagihara

发明人： Yoshio Hagihara

IPC分类号： H04N5/335

CPC分类号： H04N5/378 ,  H04N5/3658

摘要： An image pickup device may include an image pickup unit in which unit pixels having photoelectric conversion elements are arranged, the unit pixels outputting pixel signals, a reference signal generation unit, a comparison unit that includes a differential amplifier unit and a reset unit, the differential amplifier unit comparing a voltage of the first input terminal to a voltage of the second input terminal, a measurement unit that measures a comparison time of the comparison unit from a comparison start to a comparison end, and a change unit that changes the voltage of the first input terminal so that a voltage difference between the first input terminal and the second input terminal is set to a voltage at which a comparison operation by the comparison unit is ensured after a reset operation by the reset unit.

摘要翻译： 图像拾取装置可以包括其中布置有光电转换元件的单位像素的图像拾取单元，输出像素信号的单位像素，参考信号生成单元，包括差分放大器单元和复位单元的比较单元，差分 放大器单元，将第一输入端子的电压与第二输入端子的电压进行比较;测量单元，其测量比较单元从比较开始到比较结束的比较时间;以及改变单元， 第一输入端子，使得第一输入端子和第二输入端子之间的电压差被设置为在由复位单元进行的复位操作之后确保比较单元的比较操作的电压。

公开(公告)号：US07999871B2

公开(公告)日：2011-08-16

申请号：US12115055

申请日：2008-05-05

申请人： Yoshio Hagihara

发明人： Yoshio Hagihara

IPC分类号： H04N3/14

CPC分类号： H04N5/3741 ,  H04N5/347 ,  H04N5/3597

摘要： A solid-state imaging apparatus including: an image section having a plurality of pixel units arranged into a matrix, each pixel unit having at least one subunit consisting of an electric charge generation means for generating signal electric charges corresponding to the amount of incident electromagnetic wave and a signal transfer means for transferring signal electric charges generated by the electric charge generation means, an electric charge accumulation means for accumulating the transferred signal electric charges, a first reset means for resetting the electric charge accumulation means, an amplification means for amplifying a signal corresponding to signal electric charges accumulated at the electric charge accumulation means, and a select means for selectively outputting the amplified signal to a vertical signal line; and a signal transfer assisting means for making a gradient of potential in the vicinity of the electric charge generation means toward the signal transfer means to be greater at the time of transfer of the signal electric charge than at the time of non-transfer.

摘要翻译： 一种固态成像设备，包括：具有排列成矩阵的多个像素单元的图像部分，每个像素单元具有至少一个子单元，所述至少一个子单元包括电荷产生装置，用于产生对应于入射电磁波量的信号电荷 以及用于传送由电荷产生装置产生的信号电荷的信号传送装置，用于累积传送的信号电荷的电荷累积装置，用于复位电荷累积装置的第一复位装置，用于放大信号的放大装置 对应于在电荷累积装置处累积的信号电荷;以及选择装置，用于选择性地将放大的信号输出到垂直信号线; 以及信号传递辅助装置，用于使电荷发生装置附近的电位梯度朝向信号传送装置在传送信号电荷时比在不传送时更大。

公开(公告)号：US20110186713A1

公开(公告)日：2011-08-04

申请号：US13018949

申请日：2011-02-01

申请人： Yoshio Hagihara

发明人： Yoshio Hagihara

IPC分类号： H01L27/146 ,  H03K21/00

CPC分类号： H01L27/146 ,  H03K21/00

摘要： A data processing method may include counting one of a plurality of clock signals with a first mode, counting clock signals based on a predetermined number of the plurality of clock signals with the first mode, to output a first clock signal every time a counter value becomes a first predetermined value, counting the first clock signal with the first mode, counting one of the clock signals with a second mode while the counted value is considered as a first initial value, counting clock signals based on the predetermined number of the plurality of clock signals with the second mode, to output a second clock signal every time the counter value becomes a second predetermined value while the counted value is considered as a second initial value, counting the second clock signal with the second mode, and outputting the counter values with the second mode as difference data between a first data signal and a second data signal.

摘要翻译： 数据处理方法可以包括以第一模式计数多个时钟信号中的一个，基于具有第一模式的多个时钟信号的预定数量对时钟信号进行计数，以在每当计数器值变为 第一预定值，以第一模式对第一时钟信号进行计数，以第二模式计数一个时钟信号，同时将该计数值视为第一初始值，基于多个时钟的预定数量对时钟信号进行计数 信号与第二模式，以在每当计数器值变为第二预定值时输出第二时钟信号，同时将该计数值视为第二初始值，以第二模式对第二时钟信号进行计数，并且用 第二模式作为第一数据信号和第二数据信号之间的差分数据。

公开(公告)号：US20110095928A1

公开(公告)日：2011-04-28

申请号：US12994604

申请日：2009-05-22

申请人： Yoshio Hagihara

发明人： Yoshio Hagihara

IPC分类号： H03M1/50

CPC分类号： H04N5/378 ,  H03K3/0315 ,  H03K5/1504 ,  H03M1/14 ,  H03M1/502 ,  H03M1/60 ,  H04N5/3765

摘要： A clock generating circuit in which a plurality of stages of inverting circuits are connected, a start signal that causes start of clock generation and an output signal from the inverting circuit of a predetermined stage are input to one of the inverting circuits, an element having impedance that changes in accordance with a magnitude of an object analog signal that is an object of conversion to a digital signal is provided between the adjacent inverting circuits, generates a clock of a frequency in accordance with the magnitude of the object analog signal. A counter counts the number of clocks generated by the clock generating circuit and outputs a count value.

摘要翻译： 一个时钟发生电路，其中连接有多级反相电路，将启动时钟产生的起始信号和来自预定级的反相电路的输出信号输入到反相电路中的一个，具有阻抗的元件 在相邻的反相电路之间设置根据作为数字信号的转换对象的目标模拟信号的幅度的变化，根据对象模拟信号的大小产生频率的时钟。 计数器对由时钟发生电路产生的时钟数进行计数，并输出计数值。

公开(公告)号：US07692703B2

公开(公告)日：2010-04-06

申请号：US10830961

申请日：2004-04-23

申请人： Hiroshi Itoh ,  Seisuke Matsuda ,  Shigeru Hosokai ,  Yuichi Gomi ,  Yoshio Hagihara

发明人： Hiroshi Itoh ,  Seisuke Matsuda ,  Shigeru Hosokai ,  Yuichi Gomi ,  Yoshio Hagihara

IPC分类号： H04N3/14 ,  H04N5/335

CPC分类号： H04N5/3415

摘要： An image pick-up apparatus includes an image pick-up device and a filter circuit. The image pick-up device includes a pixel portion for converting a subject image into an electric signal, a scanning circuit for dividing the pixel portion into a plurality of areas, for non-linearly dividing the boundary of the areas of at least one side of the adjacent areas based on the unit of pixel, and a plurality of output circuits for individually outputting video signals. The filter circuit performs filter processing of the video signals outputted from the plurality of output circuits for the pixels near the boundary of the areas. Thus, the image quality can be improved in the multi-channel output system.

摘要翻译： 图像拾取装置包括图像拾取装置和滤波器电路。 图像拾取装置包括用于将被摄体图像转换为电信号的像素部分，用于将像素部分分成多个区域的扫描电路，用于非线性地划分至少一个方面的区域的边界 基于像素单位的相邻区域，以及用于单独输出视频信号的多个输出电路。 滤波器电路对从多个输出电路输出的视频信号对区域边界附近的像素进行滤波处理。 因此，可以在多声道输出系统中提高图像质量。