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    Reconfiguration in a multi-core processor system with configurable isolation
    52.
    发明授权
    Reconfiguration in a multi-core processor system with configurable isolation 有权
    在具有可配置隔离的多核处理器系统中重新配置

    公开(公告)号：US07966519B1

    公开(公告)日：2011-06-21

    申请号：US12250381

    申请日：2008-10-13

    申请人： Nidhi Aggarwal ,  Norman Paul Jouppi ,  Parthasararthy Ranganathan

    发明人： Nidhi Aggarwal ,  Norman Paul Jouppi ,  Parthasararthy Ranganathan

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1423 ,  G06F11/2035

    摘要： Methods and integrated circuits for reconfiguration in a multi-core processor system with configurable isolation are described. According to one embodiment, a processor configuration method includes determining that a first module is faulty. A second module is configured to communicate with the first module when the first module is not faulty. The method also includes analyzing a third module with respect to a substitution criterion, selecting the third module based on the analyzing determining that the third module satisfies the substitution criterion, and subsequent to the selecting, configuring the second module to communicate with the third module instead of the first module. Additional embodiments are described in the disclosure.

    摘要翻译： 描述了具有可配置隔离的多核处理器系统中用于重新配置的方法和集成电路。 根据一个实施例，处理器配置方法包括确定第一模块是有故障的。 第二模块被配置为当第一模块没有故障时与第一模块通信。 该方法还包括相对于替代标准分析第三模块，基于分析确定第三模块满足替代标准来选择第三模块，并且在选择之后，配置第二模块以与第三模块通信 的第一个模块。 在本公开中描述了另外的实施例。

    Reconfigurable, fault tolerant, multistage interconnect network and protocol
    53.
    发明授权
    Reconfigurable, fault tolerant, multistage interconnect network and protocol 失效
    可重配置，容错，多级互联网络和协议

    公开(公告)号：US07706361B2

    公开(公告)日：2010-04-27

    申请号：US11230340

    申请日：2005-09-20

    申请人： Robert J. McMillen ,  M. Cameron Watson ,  David J. Chura

    发明人： Robert J. McMillen ,  M. Cameron Watson ,  David J. Chura

    IPC分类号： H04Q11/00

    CPC分类号： G06F11/2005 ,  G01J3/06 ,  G06F11/1423 ,  G06F11/2007 ,  G06F11/22 ,  G06F2201/85 ,  H04L49/1515 ,  H04L49/358 ,  H04L49/552 ,  H04L49/555 ,  H04L49/557 ,  H04Q3/68 ,  H04Q2213/13332

    摘要： A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 [logb N] stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and [logb N] indicates a ceiling function providing the smallest integer not less than logb N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.

    摘要翻译： 能够支持大规模并行处理的多级互连网络（MIN），包括连接到网络的输入和输出端口的处理器模块（PM）之间的点对点和多点通信。 网络使用以2 [logb N]级布置的互连交换节点构建，其中b是交换节点输入/输出端口的数量，N是网络输入/输出端口的数量，[logb N]表示提供的上限功能 最小的整数不小于logb N.额外的级别提供网络输入端口和网络输出端口之间的额外路径，从而增强容错能力和减少争用。

    SELF-AWARE AND SELF-HEALING COMPUTING SYSTEM
    54.
    发明申请
    SELF-AWARE AND SELF-HEALING COMPUTING SYSTEM 审中-公开
    自我评估和自我治疗计算系统

    公开(公告)号：US20090138759A1

    公开(公告)日：2009-05-28

    申请号：US12358288

    申请日：2009-01-23

    申请人： Deepak K. Gangadhar

    发明人： Deepak K. Gangadhar

    IPC分类号： G06F11/277

    CPC分类号： G06F11/1423 ,  G06F11/008 ,  G06F11/3447 ,  G06F11/3452 ,  G06F11/3495 ,  G06F2201/875

    摘要： A method and a computing system for performing the method. Microstates of components of a computing system are organized into macrostates of the computing system. Each microstate represents a state that a component of the computing system is able to individually enter. Each macrostate represents a state that the computing system is able to enter as a whole. The macrostates of the computing system are organized into meta-dynamic states of the computing system. The computing system is monitored such that perturbations of the computing system are detected, wherein a perturbation of the computing system will result in movement thereof to a new meta-dynamic state. It is determined that the new meta-dynamic state is undesirable. A path is determined. The path causes the computing system to move back to a desirable meta-dynamic state. The computing system is caused to move on the path to the desirable meta-dynamic state.

    摘要翻译： 一种用于执行该方法的方法和计算系统。 计算系统的组件的微阵列被组织成计算系统的宏观状态。 每个微状态表示计算系统的组件能够单独进入的状态。 每个宏状态表示计算系统能够作为一个整体进入的状态。 计算系统的宏观状态被组织成计算系统的元动态状态。 监视计算系统，以便检测到计算系统的扰动，其中计算系统的扰动将导致其移动到新的元动态状态。 确定新的元动态状态是不期望的。 确定路径。 该路径使得计算系统移回到期望的元动态状态。 导致计算系统在所需的元动态状态的路径上移动。

    Dynamically reconfigurable interconnection
    57.
    发明申请
    Dynamically reconfigurable interconnection 有权
    动态可重配置互连

    公开(公告)号：US20030061476A1

    公开(公告)日：2003-03-27

    申请号：US09963890

    申请日：2001-09-25

    发明人： Andrew E. Phelps ,  Daniel P. Drogichen ,  Donald B. Kay

    IPC分类号： G06F001/24

    CPC分类号： G06F11/2007 ,  G06F11/1423 ,  G06F11/2038 ,  G06F2201/85

    摘要： A method and apparatus for dynamically reconfiguring a computing system are disclosed. The method comprises detecting a predetermined condition triggering a reconfiguration of the computing system; and dynamically reconfiguring a signal path affected by the condition from a first mode to a second mode responsive to detecting the condition. The apparatus is a computing system, comprising: a plurality of I/O switches, a crossbar switch, a plurality of signal paths; and a system controller. Each signal path is defined by an I/O switch and the crossbar switch. The system controller is capable of detecting a predetermined condition triggering a reconfiguration and dynamically reconfiguring at least one of the signal paths affected by the condition from a first mode to a second mode.

    摘要翻译： 公开了一种用于动态重新配置计算系统的方法和装置。 该方法包括检测触发计算系统的重新配置的预定条件; 以及响应于检测到所述条件，将受所述条件影响的信号路径从第一模式动态重新配置到第二模式。 该装置是一种计算系统，包括：多个I / O开关，纵横开关，多个信号路径; 和系统控制器。 每个信号路径由I / O开关和交叉开关定义。 系统控制器能够检测触发重新配置的预定条件，并且动态地重新配置受从第一模式到第二模式的条件影响的信号路径中的至少一个。

    System for flushing high-speed serial link buffers by ignoring received data and using specially formatted requests and responses to identify potential failure
    58.
    发明授权
    System for flushing high-speed serial link buffers by ignoring received data and using specially formatted requests and responses to identify potential failure 失效
    通过忽略接收到的数据并使用特殊格式的请求和响应来识别潜在故障的系统来冲洗高速串行链路缓冲区

    公开(公告)号：US06125407A

    公开(公告)日：2000-09-26

    申请号：US123993

    申请日：1998-07-29

    申请人： Jack Abily ,  Yu Jun Jean Qian

    发明人： Jack Abily ,  Yu Jun Jean Qian

    IPC分类号： G06F13/00 ,  G06F11/14 ,  H04L29/02 ,  G06F13/14

    CPC分类号： G06F11/1423 ,  G06F13/4059

    摘要： A process and system for flushing high-speed buffers in a serial link used between a mover circuit (4) that executes data move operations and at least two memories through at least two channels (400, 401), the data move operations each being constituted by a move request followed by the return of a response or acknowledgement of the request, cyclically with interlacing, the responses following the same pair of serial channels (400, 401) as the requests for which they constitute the acknowledgements. The process comprises:a step for placing the mover circuit (4) into a so-called "absorption" mode of operation,a step for generating a specific write request and a specific read request, each of which comprises a so-called "barrier" marker contained in a control character preceding or following the request,a step for accumulating the responses received, anda step for comparing the responses received.

    摘要翻译： 一种在通过至少两个通道（400,401）执行数据移动操作的移动电路（4）和至少两个存储器之间的串行链路中冲洗高速缓冲器的过程和系统，每个构成的数据移动操作 通过移动请求，随后循环地返回对请求的响应或确认，其中交织是与构成确认的请求相同的串行通道对（400,401）之后的响应。 该方法包括：将移动器电路（4）置于所谓的“吸收”操作模式的步骤，用于产生特定写入请求和特定读取请求的步骤，每个步骤包括所谓的“屏障 “包含在请求之前或之后的控制字符中的标记，用于累积接收到的响应的步骤，以及用于比较接收到的响应的步骤。

    Deadlock avoidance method in a computer network
    59.
    发明授权
    Deadlock avoidance method in a computer network 失效
    计算机网络中的死锁回避方法

    公开(公告)号：US06065063A

    公开(公告)日：2000-05-16

    申请号：US15593

    申请日：1998-01-29

    申请人： Bulent Abali

    发明人： Bulent Abali

    IPC分类号： G06F11/00

    CPC分类号： G06F15/17375 ,  G06F11/1423

    摘要： In an apparatus having a network including successive stages of cross-point switches which collectively interconnect a plurality of nodes external to said network, wherein at least one message is carried between one of the nodes and one of the cross-point switches over a route through said network, a method for preventing routing deadlocks from occurring in the network which comprises the steps of: creating a graphical representation of the network; searching for the existence of cycles within the graphical representation; partitioning the graphical representation into at a first subgraph and a second subgraph if cycles exist in the graphical representation; searching for the existence of edges directed from the first subgraph to the second subgraph; and removing the edges directed from the first subgraph to the second subgraph. Preferably the step of partitioning the network into at a first subgraph and a second subgraph is performed such that the first subgraph and the second subgraph have an equal number of vertices, a number of directed edges from the first subgraph to the second subgraph is minimized so as to minimize the number of routes prohibited, and a set of partition constraints are satisfied. The method is recursively applied to the first subgraph and then the second subgraph, thereby removing all of the deadlock prone cycles in the network while minimizing the number of routes prohibited due to remove edges.

    摘要翻译： 在具有网络的设备中，该网络包括将所述网络外部的多个节点共同互连的交叉点交换机的连续级，其中，在一个节点与一个交叉点交换机之间通过一条路由上携带至少一个消息 所述网络是防止网络中发生路由死锁的方法，包括以下步骤：创建网络的图形表示; 在图形表示中搜索循环的存在; 如果在图形表示中存在周期，则将图形表示分割成第一子图和第二子图; 搜索从第一子图指向的第二子图的边缘的存在; 以及将从第一子图指向的边缘移除到第二子图。 优选地，将网络划分成第一子图和第二子图的步骤被执行，使得第一子图和第二子图具有相等数量的顶点，从第一子图到第二子图的多个有向边被最小化 以最小化禁止的路由数量，并且满足一组分区约束。 该方法递归地应用于第一子图，然后递归地应用于第二子图，从而消除网络中的所有死锁倾向周期，同时最小化由于移除边缘而禁止的路由的数量。

    Re-synchronization system using common memory bus to transfer restart data from non-faulty processor to failed processor
    60.
    发明授权
    Re-synchronization system using common memory bus to transfer restart data from non-faulty processor to failed processor 失效
    使用公共存储器总线的重新同步系统将重启数据从非故障处理器传输到故障处理器

    公开(公告)号：US4757442A

    公开(公告)日：1988-07-12

    申请号：US874704

    申请日：1986-06-16

    申请人： Hironobu Sakata

    发明人： Hironobu Sakata

    IPC分类号： G06F11/14 ,  G06F11/16 ,  G06F11/00 ,  G06F11/30

    CPC分类号： G06F11/1658 ,  G06F11/1423 ,  G06F11/1679

    摘要： A multi-processing device includes three or more processing systems, each having a processor and a corresponding main memory connected to each other by means of an individual memory bus. The multi-processing device also includes a common memory bus connectable to all the processors and all the main memories of the respective systems, an asynchronism detection circuit connected to the respective processors to produce an asynchronism detection signal indicating which system or systems are in asynchronous state, and a device control circuit responsive to the asynchronism detection signal to send a common memory bus select signal to the main memory of each failed system to change its bus connection from the individual memory bus to the common memory bus. The device control circuit also generates a master designation signal for allowing an arbitrary processor of the normal non-faulty systems to be designated as a master processor, and a copy request signal to the respective processors. The copy request signal causes the master processor to copy the content of the main memory of the normal system to the main memory of each failed system. When the synchronization between the respective systems is established, the device control circuit outputs a restart request signal to the respective processors, thus initiating the execution from a fixed, stored address in a control memory of each processor to enable synchronous starting of all of the processor. The multi-processing device further includes a communication control circuit connected to the common memory bus, thus permitting parallel loading of an initial program to the main memories of the respective systems for achieving recovery in the case where all the systems are asynchronous with each other.

    摘要翻译： 多处理装置包括三个或更多个处理系统，每个处理系统具有通过单独的存储器总线相互连接的处理器和对应的主存储器。 多处理装置还包括可连接到所有处理器和各个系统的所有主存储器的公共存储器总线，连接到各个处理器的异步检测电路，以产生指示哪个系统或系统处于异步状态的异步检测信号 以及响应于异步检测信号的设备控制电路，以向每个故障系统的主存储器发送公共存储器总线选择信号，以将其总线连接从单独存储器总线改变为公共存储器总线。 设备控制电路还产生主指定信号，用于允许将正常非故障系统的任意处理器指定为主处理器，并将复制请求信号指定给各个处理器。 复制请求信号使得主处理器将正常系统的主存储器的内容复制到每个故障系统的主存储器。 当建立各个系统之间的同步时，设备控制电路向各个处理器输出重新启动请求信号，从而从每个处理器的控制存储器中的固定的存储地址启动执行，以使所有处理器能够同步启动 。 多处理装置还包括连接到公共存储器总线的通信控制电路，从而允许将初始程序并行加载到各个系统的主存储器，以在所有系统彼此异步的情况下实现恢复。