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公开(公告)号：US06944711B2
公开(公告)日：2005-09-13
申请号：US10646699
申请日：2003-08-25
Applicant: Kazuhiko Mogi , Norifumi Nishikawa , Yoshiaki Eguchi
Inventor： Kazuhiko Mogi , Norifumi Nishikawa , Yoshiaki Eguchi
CPC classification number: G06F12/0871 , G06F12/0873 , G06F12/12 , G06F2212/282 , Y10S707/99953
Abstract: A cache management method disclosed herein enables optimal cache space settings to be provided on a storage device in a computer system where database management systems (DBMSs) run. Through the disclosed method, cache space partitions to be used per data set are set, based on information about processes to be executed by the DBMSs, which is given as design information. For example, based on estimated rerun time of processes required after DBMS abnormal termination, cache space is adjusted to serve the needs of logs to be output from the DBMS. In another example, initial cache space allocations for table and index data is optimized, based on process types and approximate access characteristics of data. In yet another example, from a combination of results of pre-analysis of processes and cache operating statistics information, a change in process execution time by cache space tuning is estimated and a cache effect is enhanced.
Abstract translation: 本文公开的高速缓存管理方法使得能够在数据库管理系统（DBMS）运行的计算机系统中的存储设备上提供最佳高速缓存空间设置。 通过所公开的方法，基于由作为设计信息给出的由DBMS执行的处理的信息来设置要针对每个数据集使用的高速缓存空间分区。 例如，基于在DBMS异常终止之后所需的进程的估计重新运行时间，调整缓存空间以满足要从DBMS输出的日志的需要。 在另一个示例中，基于数据的过程类型和近似访问特征来优化表和索引数据的初始高速缓存空间分配。 在另一个示例中，根据进程预分析和高速缓存操作统计信息的结果的组合，估计通过高速缓存空间调整的处理执行时间的改变，并且提高高速缓存效果。
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公开(公告)号：US20040193803A1
公开(公告)日：2004-09-30
申请号：US10646699
申请日：2003-08-25
Inventor： Kazuhiko Mogi , Norifumi Nishikawa , Yoshiaki Eguchi
IPC: G06F012/00
CPC classification number: G06F12/0871 , G06F12/0873 , G06F12/12 , G06F2212/282 , Y10S707/99953
Abstract: A cache management method disclosed herein enables optimal cache space settings to be provided on a storage device in a computer system where database management systems (DBMSs) run. Through the disclosed method, cache space partitions to be used per data set are set, based on information about processes to be executed by the DBMSs, which is given as design information. For example, based on estimated rerun time of processes required after DBMS abnormal termination, cache space is adjusted to serve the needs of logs to be output from the DBMS. In another example, initial cache space allocations for table and index data is optimized, based on process types and approximate access characteristics of data. In yet another example, from a combination of results of pre-analysis of processes and cache operating statistics information, a change in process execution time by cache space tuning is estimated and a cache effect is enhanced.
Abstract translation: 本文公开的高速缓存管理方法使得能够在数据库管理系统（DBMS）运行的计算机系统中的存储设备上提供最佳高速缓存空间设置。 通过所公开的方法，基于由作为设计信息给出的由DBMS执行的处理的信息来设置要针对每个数据集使用的高速缓存空间分区。 例如，基于在DBMS异常终止之后所需的进程的估计重新运行时间，调整缓存空间以满足要从DBMS输出的日志的需要。 在另一个示例中，基于数据的过程类型和近似访问特征来优化表和索引数据的初始高速缓存空间分配。 在另一个示例中，根据进程预分析和高速缓存操作统计信息的结果的组合，估计通过高速缓存空间调整的处理执行时间的改变，并且提高高速缓存效果。
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公开(公告)号：US20240211404A1
公开(公告)日：2024-06-27
申请号：US18600971
申请日：2024-03-11
Applicant: Roku, Inc.
Inventor： Bill ATARAS
IPC: G06F12/084 , G06F8/65 , G06F8/656 , G06F12/0873 , G06F16/957
CPC classification number: G06F12/084 , G06F8/65 , G06F8/656 , G06F12/0873 , G06F16/9574 , G06F2212/1008 , G06F2212/1048 , G06F2212/163 , G06F2212/282 , G06F2212/313 , G06F2212/314 , G06F2212/62
Abstract: Disclosed herein are system, apparatus, article of manufacture, method, and/or computer program product embodiments for providing rolling updates of distributed systems with a shared cache. An embodiment operates by receiving a data item key corresponding to a request from a user profile operating on a computing device and receiving a version identifier corresponding to a first version of an application operating on the computing device. It is determined that a shared cache includes a first value and second value for the data item key. A key component is generated corresponding to the user profile. Both the generated key component and the data item key are provided to the shared cache, and the first value of the data item as stored in the shared cache is received. The first value of the first version of the data item is updated.
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公开(公告)号：US11797474B2
公开(公告)日：2023-10-24
申请号：US17079465
申请日：2020-10-24
Applicant: Hyperion Core, Inc.
Inventor： Martin Vorbach
IPC: G06F15/78 , G06F9/30 , G06F9/345 , G06F9/38 , G06F12/0893 , G11C8/16 , G11C11/412 , G06F8/41 , G06F12/0877
CPC classification number: G06F15/7839 , G06F9/3017 , G06F9/30043 , G06F9/345 , G06F9/38 , G06F12/0893 , G06F15/7821 , G06F8/4441 , G06F8/452 , G06F12/0877 , G06F2212/2515 , G06F2212/282 , G06F2213/0038 , G11C8/16 , G11C11/412 , Y02D10/00
Abstract: Implementations relate to a data processor that includes a data processing unit having a plurality of processing elements and a cache hierarchy including a plurality of levels of data caches. The data caches include a first level data cache connected to a second level data cache, and a main memory connected to the highest level cache of the cache hierarchy. At least one of the first level data cache or second level data cache is divided into a plurality of cache segments, and during operation of the data processor, at least some of the plurality of cache segments are excluded from cache operation. Each of the excluded cache segments is dedicated to an associated processing element as tightly coupled local access memory.
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公开(公告)号：US20190196783A1
公开(公告)日：2019-06-27
申请号：US15851480
申请日：2017-12-21
Applicant: International Business Machines Corporation
Inventor： Carlos Henrique Andrade Costa , Abdullah Kayi , Yoonho Park , Charles Johns
IPC: G06F7/08 , G06F17/30 , G06F12/0846
CPC classification number: G06F7/08 , G06F12/0848 , G06F16/2228 , G06F16/2372 , G06F16/24554 , G06F2212/282
Abstract: Methods and systems for shuffling data are described. A processor may generate pair data from source data. The processor may insert the pair data into local tuple spaces. In response to a request for a particular key, the processor may determine a presence of the requested key in a global tuple space. The processor may, in response to a presence of the requested key in the global tuple space, update the global tuple space. The update may be based on the pair data among the local tuple spaces including the existing key. The processor may, in response to an absence of the requested key in the global tuple space, insert pair data including the missing key from the local tuple spaces into the global tuple space. The processor may fetch the requested pair data, and may shuffle the fetched data to generate a dataset.
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公开(公告)号：US20190121423A1
公开(公告)日：2019-04-25
申请号：US16223818
申请日：2018-12-18
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Efraim Rotem , Eliezer Weissmann , Doron Rajwan , Nadav Shulman , Alon Naveh , Hisham Abu-Salah
IPC: G06F1/3234 , G06F1/3287 , G06F12/084 , G06F12/0802 , G06F1/28 , G06F12/0864 , G06F12/0846
CPC classification number: G06F1/3275 , G06F1/28 , G06F1/3287 , G06F12/0802 , G06F12/084 , G06F12/0848 , G06F12/0864 , G06F2212/1028 , G06F2212/282 , G06F2212/502 , G06F2212/621 , Y02D10/13
Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
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公开(公告)号：US20190121422A1
公开(公告)日：2019-04-25
申请号：US16223794
申请日：2018-12-18
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Efraim Rotem , Eliezer Weissmann , Doron Rajwan , Nadav Shulman , Alon Naveh , Hisham Abu-Salah
IPC: G06F1/3234 , G06F1/3287 , G06F12/084 , G06F12/0802 , G06F1/28 , G06F12/0864 , G06F12/0846
CPC classification number: G06F1/3275 , G06F1/28 , G06F1/3287 , G06F12/0802 , G06F12/084 , G06F12/0848 , G06F12/0864 , G06F2212/1028 , G06F2212/282 , G06F2212/502 , G06F2212/621 , Y02D10/13
Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
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公开(公告)号：US20190057042A1
公开(公告)日：2019-02-21
申请号：US15680732
申请日：2017-08-18
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Kyler A. Anderson , Kevin J. Ash , Matthew G. Borlick , Lokesh M. Gupta
IPC: G06F12/126 , G06F12/0891 , G06F12/0895
CPC classification number: G06F12/126 , G06F12/0842 , G06F12/0846 , G06F12/0868 , G06F12/0891 , G06F12/0895 , G06F2212/1024 , G06F2212/1044 , G06F2212/154 , G06F2212/262 , G06F2212/263 , G06F2212/282 , G06F2212/312
Abstract: Provided are techniques for destaging pinned retryable data in cache. A ranks scan structure is created with an indicator for each rank of multiple ranks that indicates whether pinned retryable data in a cache for that rank is destageable. A cache directory is partitioned into chunks, wherein each of the chunks includes one or more tracks from the cache. A number of tasks are determined for the scan of the cache. The number of tasks are executed to scan the cache to destage pinned retryable data that is indicated as ready to be destaged by the ranks scan structure, wherein each of the tasks selects an unprocessed chunk of the cache directory for processing until the chunks of the cache directory have been processed.
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公开(公告)号：US20190057037A1
公开(公告)日：2019-02-21
申请号：US15680577
申请日：2017-08-18
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Kyler A. Anderson , Kevin J. Ash , Lokesh M. Gupta
IPC: G06F12/0895
CPC classification number: G06F12/0895 , G06F2212/1024 , G06F2212/1041 , G06F2212/282
Abstract: A list of a first type of tracks in a cache is generated. A list of a second type of tracks in the cache is generated, wherein I/O operations are completed relatively faster to the first type of tracks than to the second type of tracks. A determination is made as to whether to demote a track from the list of the first type of tracks or from the list of the second type of tracks.
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公开(公告)号：US20180314639A1
公开(公告)日：2018-11-01
申请号：US15581963
申请日：2017-04-28
Applicant: EMC IP Holding Company LLC
Inventor： Todd Wilde , Samir Rajadnya , Karthik Ramachandran , Michael Nishimoto
IPC: G06F12/0864
CPC classification number: G06F12/0864 , G06F12/0868 , G06F12/0871 , G06F12/0893 , G06F12/123 , G06F2212/282 , G06F2212/313 , G06F2212/608
Abstract: In general, embodiments of the technology relate to a method and system for storing and reading data from persistent storage. More specifically, embodiments of the technology relate to a method and system for storing data in persistent storage, where the data written to the persistent storage is not immediately accessible in the persistent storage (i.e., during the inaccessibility period). In such instances, embodiments of the technology provide a method and system to enable the storage system to service read requests for the data using a primary cache entry table (PCET) and an overflow table.
