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公开(公告)号：US20170200692A1
公开(公告)日：2017-07-13
申请号：US15472912
申请日：2017-03-29
Applicant: General Electric Company
Inventor： Arun Virupaksha Gowda , Paul Alan McConnelee
IPC: H01L23/00 , H01L23/522 , H01L21/78 , H01L25/00 , H01L21/768 , H01L21/683 , H01L23/528 , H01L25/07
CPC classification number: H01L24/46 , H01L21/6835 , H01L21/76879 , H01L21/78 , H01L23/3164 , H01L23/5226 , H01L23/525 , H01L23/528 , H01L23/5283 , H01L23/564 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/82 , H01L24/85 , H01L25/072 , H01L25/50 , H01L2224/03466 , H01L2224/04042 , H01L2224/05018 , H01L2224/05093 , H01L2224/05094 , H01L2224/05124 , H01L2224/05147 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/24137 , H01L2224/29101 , H01L2224/32225 , H01L2224/45015 , H01L2224/45147 , H01L2224/48137 , H01L2224/4847 , H01L2224/48847 , H01L2224/4903 , H01L2224/4911 , H01L2224/73265 , H01L2224/8203 , H01L2224/83424 , H01L2224/83447 , H01L2924/00014 , H01L2924/07025 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/1203 , H01L2924/1301 , H01L2924/1302 , H01L2924/13023 , H01L2924/13034 , H01L2924/1304 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/014 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/00 , H01L2224/45099 , H01L2924/207
Abstract: A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.
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公开(公告)号：US20170194237A1
公开(公告)日：2017-07-06
申请号：US15465433
申请日：2017-03-21
Applicant: Navitas Semiconductor, Inc.
Inventor： Daniel Marvin Kinzer
IPC: H01L23/495 , H01L23/00 , H02M3/158 , H01L25/00 , H01L21/56 , H01L23/31 , H01L25/065
CPC classification number: H01L23/49575 , H01L21/561 , H01L23/3107 , H01L23/3114 , H01L23/49503 , H01L23/49541 , H01L23/49548 , H01L23/49562 , H01L23/49589 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L24/97 , H01L25/0655 , H01L25/072 , H01L25/16 , H01L25/50 , H01L2224/04042 , H01L2224/05014 , H01L2224/05554 , H01L2224/0612 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48137 , H01L2224/4814 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/48479 , H01L2224/49113 , H01L2224/49175 , H01L2224/85051 , H01L2224/85186 , H01L2924/00014 , H01L2924/1033 , H01L2924/1304 , H01L2924/1306 , H01L2924/14 , H01L2924/1425 , H01L2924/1426 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H02M3/158 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599 , H01L2924/00
Abstract: Leadless electronic packages for GaN-based half bridge power conversion circuits have low inductance internal and external connections, high thermal conductivity and a large separation between external connections for use in high voltage power conversion circuits. Some electronic packages employ “L” shaped power paths and internal low impedance die to die connections. Further embodiments employ an insulative substrate disposed within the electronic package for efficient power path routing and increased packaging density.
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公开(公告)号：US09698130B2
公开(公告)日：2017-07-04
申请号：US15272568
申请日：2016-09-22
Inventor： Gerald Weis , Christian Vockenberger , Roland Sekavcnik
IPC: H01L23/34 , H01L25/16 , H01L23/467 , H01L23/538 , H01L23/00 , H01L25/07 , H05K1/02 , H05K1/11 , H05K1/18 , H05K7/20 , H01L23/367 , H01L25/10
CPC classification number: H01L25/16 , H01L23/3677 , H01L23/467 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/17 , H01L24/19 , H01L24/20 , H01L25/074 , H01L25/105 , H01L2223/6677 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/2518 , H01L2225/1035 , H01L2225/1047 , H01L2225/1094 , H01L2924/1033 , H01L2924/13055 , H01L2924/1306 , H01L2924/1426 , H01L2924/1436 , H01L2924/153 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19102 , H01L2924/19105 , H05K1/0206 , H05K1/0209 , H05K1/0212 , H05K1/0298 , H05K1/115 , H05K1/181 , H05K1/185 , H05K7/20154 , H05K2201/10015 , H05K2201/10166 , Y02P70/611
Abstract: In a connection system for electronic components (1) comprising a plurality of insulating layers (2) and conductive layers (3) and further comprising at least one embedded electronic component (4) embedded within at least one of the plurality of insulating layers (2) and conductive layers (3) the at least one embedded electronic component (4) is at least one first transistor having a bulk terminal thereof in thermal contact with a thermal duct (6) comprised of a plurality of vias (7) reaching through at least one of an insulating layer (2) and a conductive layer (3) of the connection system for electronic components (1) and emerging on a first outer surface (8) of the connection system for electronic components (1) under a first surface-mounted component (10).
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公开(公告)号：US20170179265A1
公开(公告)日：2017-06-22
申请号：US15300583
申请日：2014-07-04
Applicant: Mitsubishi Electric Corporation
Inventor： Kenji HATORI , Shuichi KITAMURA , Tetsuo MOTOMIYA
IPC: H01L29/739 , H01L29/20 , H01L23/373 , H01L29/16
CPC classification number: H01L29/7393 , H01L23/3736 , H01L23/48 , H01L25/072 , H01L25/18 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L2224/04026 , H01L2224/04042 , H01L2224/06181 , H01L2224/291 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2224/49175 , H01L2224/73265 , H01L2924/00014 , H01L2924/10254 , H01L2924/10272 , H01L2924/1033 , H01L2924/1203 , H01L2924/13055 , H01L2924/014 , H01L2924/00012 , H01L2224/45099
Abstract: An object is to provide a technique that enables suppression of oscillation of a gate signal waveform. A power semiconductor device includes a power semiconductor chip, a plurality of collector main terminals and a plurality of emitter main terminals electrically connected to the power semiconductor chip, and a signal line. The plurality of collector main terminals and the plurality of emitter main terminals have protrusion portions which protrude from a disposition surface of the power semiconductor chip, respectively, and the signal line surrounds, with respect to these protrusion portions, an entire circumference of all the protrusion portions and is spaced apart therefrom in plan view.
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55.发明申请
公开(公告)号：US20170170149A1
公开(公告)日：2017-06-15
申请号：US15431649
申请日：2017-02-13
Applicant: Micron Technology, Inc.
Inventor： Seng Kim Ye , Hong Wan Ng
IPC: H01L25/065 , G06F13/16 , H01L25/00 , H01L23/31 , H01L23/00
CPC classification number: H01L25/0657 , G06F13/1668 , G06F13/1694 , H01L22/14 , H01L23/3128 , H01L23/3135 , H01L24/04 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/03 , H01L25/18 , H01L25/50 , H01L2224/04042 , H01L2224/13083 , H01L2224/1319 , H01L2224/16225 , H01L2224/291 , H01L2224/2919 , H01L2224/29294 , H01L2224/2939 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2224/81855 , H01L2224/81856 , H01L2224/83191 , H01L2224/83855 , H01L2224/83874 , H01L2224/92227 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06565 , H01L2924/00014 , H01L2924/10253 , H01L2924/1033 , H01L2924/14 , H01L2924/143 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/1443 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2924/00012 , H01L2224/45099 , H01L2924/00 , H01L2224/83101 , H01L2924/0665 , H01L2924/014 , H01L2224/83
Abstract: Semiconductor devices with controllers under stacks of semiconductor packages and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate, a controller attached to the package substrate, and at least two semiconductor packages disposed over the controller. Each semiconductor package includes a plurality of semiconductor dies. The semiconductor device further includes an encapsulant material encapsulating the controller and the at least two semiconductor packages.
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公开(公告)号：US20170170097A1
公开(公告)日：2017-06-15
申请号：US15340898
申请日：2016-11-01
Applicant: FUJI ELECTRIC CO., LTD.
Inventor： Ryohei MAKINO , Motoyoshi KUBOUCHI
IPC: H01L23/467 , H01L23/367
CPC classification number: H01L23/467 , H01L23/3672 , H01L25/115 , H01L29/1608 , H01L29/2003 , H01L2924/10272 , H01L2924/1033
Abstract: A power unit cooling body includes a base part on which a first power semiconductor module and a second power semiconductor module are mounted. A cooling body is mounted on a side of the base part opposite the first power semiconductor module and the second power semiconductor module. A height of a fin of the cooling body is configured to be made shorter on the windward side than on the leeward side.
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公开(公告)号：US20170162538A1
公开(公告)日：2017-06-08
申请号：US15441741
申请日：2017-02-24
Applicant: EV GROUP E. THALLNER GMBH
Inventor： Markus WIMPLINGER
CPC classification number: H01L24/83 , B81C3/001 , B81C2203/036 , H01L24/29 , H01L24/32 , H01L2224/29082 , H01L2224/291 , H01L2224/29105 , H01L2224/29111 , H01L2224/29116 , H01L2224/29117 , H01L2224/29118 , H01L2224/29123 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29157 , H01L2224/2916 , H01L2224/29166 , H01L2224/29169 , H01L2224/29171 , H01L2224/29184 , H01L2224/32145 , H01L2224/32507 , H01L2224/8302 , H01L2224/83022 , H01L2224/8381 , H01L2224/83894 , H01L2924/01003 , H01L2924/01005 , H01L2924/01011 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01034 , H01L2924/01037 , H01L2924/01038 , H01L2924/0105 , H01L2924/01052 , H01L2924/01055 , H01L2924/01056 , H01L2924/01322 , H01L2924/10251 , H01L2924/10252 , H01L2924/10253 , H01L2924/1026 , H01L2924/10271 , H01L2924/10272 , H01L2924/10323 , H01L2924/10328 , H01L2924/10329 , H01L2924/1033 , H01L2924/10331 , H01L2924/10332 , H01L2924/10333 , H01L2924/10334 , H01L2924/10335 , H01L2924/10336 , H01L2924/10346 , H01L2924/1037 , H01L2924/10371 , H01L2924/10372 , H01L2924/10373 , H01L2924/10375 , H01L2924/10376 , H01L2924/10377 , H01L2924/10821 , H01L2924/10823 , H01L2924/10831 , H01L2924/00 , H01L2924/00014 , H01L2924/01032 , H01L2924/01013 , H01L2924/01031 , H01L2924/0103
Abstract: A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.
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公开(公告)号：US09666569B2
公开(公告)日：2017-05-30
申请号：US14815378
申请日：2015-07-31
Inventor： Woojin Chang
IPC: H01L25/18 , H01L23/492 , H01L27/108 , H01L29/94 , H01L29/66 , H01L25/07 , H01L23/00 , H01L23/495 , H01L23/498
CPC classification number: H01L25/18 , H01L23/492 , H01L23/49562 , H01L23/49575 , H01L23/49844 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2224/48137 , H01L2224/48177 , H01L2924/00014 , H01L2924/1033 , H01L2924/13091 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Provided is switch circuit including first and second transistors, a source pad connected to a second node of the second transistor through a first signal path and connected to a gate node of the first transistor through a second signal path, a gate pad connected to a gate node of the second transistor through a third signal path; and a drain pad connected to a first node of the first transistor through a fourth signal path, wherein a second node of the first transistor and a first node of the second transistor are connected to each other through a fifth signal path, and the gate node of the first transistor and the second node of the second transistor are connected to each other through a sixth signal path separated from the first and second signal paths.
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公开(公告)号：US20170148705A1
公开(公告)日：2017-05-25
申请号：US15425614
申请日：2017-02-06
Applicant: Infineon Techonologies Americas Corp.
Inventor： Eung San Cho
IPC: H01L23/367 , H01L23/00 , H01F1/03 , H01L23/498 , H01F27/24 , H01L25/18 , H01L23/31
CPC classification number: H01L23/3675 , H01F1/0306 , H01F27/24 , H01L23/13 , H01L23/3121 , H01L23/49822 , H01L23/49838 , H01L23/5383 , H01L23/645 , H01L24/31 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/072 , H01L25/18 , H01L2224/2919 , H01L2224/32013 , H01L2224/32245 , H01L2224/32265 , H01L2224/37124 , H01L2224/37144 , H01L2224/37147 , H01L2224/40245 , H01L2224/41173 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48106 , H01L2224/48108 , H01L2224/48227 , H01L2224/48245 , H01L2224/49173 , H01L2224/73263 , H01L2224/73265 , H01L2224/83424 , H01L2224/83447 , H01L2224/84424 , H01L2224/84447 , H01L2224/84801 , H01L2224/8484 , H01L2224/8485 , H01L2224/85424 , H01L2224/85447 , H01L2924/0665 , H01L2924/10253 , H01L2924/1033 , H01L2924/13055 , H01L2924/13064 , H01L2924/13091 , H01L2924/14252 , H01L2924/1426 , H01L2924/1427 , H01L2924/15724 , H01L2924/15747 , H01L2924/19011 , H01L2924/19042 , H01L2924/19102 , H05K1/0209 , H05K1/165 , H05K1/181 , H05K1/184 , H05K1/185 , H05K2201/1003 , H05K2201/10166 , H01L2924/00014
Abstract: A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding around a core, and coupled to the semiconductor die. The winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in the PCB. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.
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公开(公告)号：US09661716B2
公开(公告)日：2017-05-23
申请号：US14838011
申请日：2015-08-27
Applicant: Nthdegree Technologies Worldwide Inc.
Inventor： Bradley S. Oraw
CPC classification number: H05B33/0857 , H01L24/24 , H01L24/82 , H01L27/15 , H01L33/0041 , H01L2224/24137 , H01L2224/32225 , H01L2224/73267 , H01L2924/10272 , H01L2924/1033 , H01L2924/12035 , H01L2924/12041 , H01L2924/12042 , H01L2924/1301 , H01L2924/13033 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13063 , H01L2924/13064 , H01L2924/13091 , H05B33/083 , H01L2924/00
Abstract: LED modules are disclosed having a control MOSFET, or other transistor, in series with an LED. In one embodiment, a MOSFET wafer is bonded to an LED wafer and singulated to form thousands of active 3-terminal LED modules with the same footprint as a single LED. Despite the different forward voltages of red, green, and blue LEDs, RGB modules may be connected in parallel and their control voltages staggered at 60 Hz or greater to generate a single perceived color, such as white. The RGB modules may be connected in a panel for general illumination or for a color display. A single dielectric layer in a panel may encapsulate all the RGB modules to form a compact and inexpensive panel. Various addressing techniques are described for both a color display and a lighting panel. Various circuits are described for reducing the sensitivity of the LED to variations in input voltage.
