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公开(公告)号：US20190158031A1
公开(公告)日：2019-05-23
申请号：US16250889
申请日：2019-01-17
申请人： pSemi Corporation
发明人： Jonathan James Klaren , David Kovac , Eric S. Shapiro , Christopher C. Murphy , Robert Mark Englekirk , Keith Bargroff , Tero Tapio Ranta
CPC分类号： H03F1/223 , H03F1/301 , H03F1/56 , H03F3/193 , H03F3/195 , H03F3/213 , H03F3/245 , H03F2200/102 , H03F2200/105 , H03F2200/165 , H03F2200/18 , H03F2200/21 , H03F2200/222 , H03F2200/225 , H03F2200/243 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/42 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/498 , H03F2200/555 , H03F2200/61 , H03F2200/78
摘要： Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
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公开(公告)号：US20180323821A1
公开(公告)日：2018-11-08
申请号：US15968927
申请日：2018-05-02
发明人： Laurent CHABERT , Raphael PAULIN
CPC分类号： H04B1/48 , H03F1/26 , H03F1/523 , H03F3/195 , H03F3/72 , H03F2200/06 , H03F2200/114 , H03F2200/181 , H03F2200/222 , H03F2200/231 , H03F2200/27 , H03F2200/294 , H03F2200/321 , H03F2200/396 , H03F2200/451 , H03F2200/489 , H03F2200/507 , H03F2200/519 , H03F2200/525 , H03F2200/61 , H03F2200/75 , H04B1/1615 , H04B1/18
摘要： A communications device includes a transmission chain coupled to an antenna a receiver chain coupled to the antenna. The receiver chain includes an amplifier device having an input coupled to the antenna. A controlled switching circuit is included in the amplifier device and is operable to selectively disconnect conduction terminals of an amplifying transistor from power supply terminals when the transmission chain is operating to pass a transmit signal to the antenna.
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公开(公告)号：US20180175807A1
公开(公告)日：2018-06-21
申请号：US15895863
申请日：2018-02-13
申请人： pSemi Corporation
发明人： Hossein Noori , Chih-Chieh Cheng
CPC分类号： H03F1/3205 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/18 , H03F2200/21 , H03F2200/211 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/24 , H03F2200/243 , H03F2200/249 , H03F2200/27 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/312 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/417 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/495 , H03F2200/546 , H03F2200/72 , H03F2200/75 , H03G1/0029 , H03G1/0088 , H03G1/0094 , H03G3/001 , H03G3/008 , H03G3/10 , H03G2201/106 , H03G2201/307 , H03G2201/504
摘要： A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
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公开(公告)号：US09929701B1
公开(公告)日：2018-03-27
申请号：US15272103
申请日：2016-09-21
发明人： Hossein Noori , Chih-Chieh Cheng
CPC分类号： H03F1/3205 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/18 , H03F2200/21 , H03F2200/211 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/24 , H03F2200/243 , H03F2200/249 , H03F2200/27 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/312 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/417 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/495 , H03F2200/546 , H03F2200/72 , H03F2200/75 , H03G1/0029 , H03G1/0088 , H03G1/0094 , H03G3/001 , H03G3/008 , H03G3/10 , H03G2201/106 , H03G2201/307 , H03G2201/504
摘要： A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
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公开(公告)号：US09929698B2
公开(公告)日：2018-03-27
申请号：US13841239
申请日：2013-03-15
CPC分类号： H03F1/223 , H01L27/0255 , H02H9/046 , H03F1/523 , H03F3/193 , H03F2200/489
摘要： An apparatus is described. The apparatus includes an input device. The apparatus also includes a positive supply voltage pad. The apparatus further includes an input signal pad. The apparatus also includes a ground pad. The apparatus further includes charged-device model protection circuitry that protects the input device from electrostatic discharge. The charged-device model protection circuitry includes at least one of de-Q circuitry and a cascode device.
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公开(公告)号：US20180069742A1
公开(公告)日：2018-03-08
申请号：US15647275
申请日：2017-07-12
申请人： MEDIATEK INC.
发明人： Chien-Cheng Lin , Ming-Da Tsai
CPC分类号： H04L27/366 , H03C3/08 , H03D7/166 , H03F1/14 , H03F1/3205 , H03F1/3211 , H03F1/3264 , H03F3/21 , H03F3/45179 , H03F3/45183 , H03F2200/21 , H03F2200/213 , H03F2200/228 , H03F2200/249 , H03F2200/471 , H03F2200/489 , H03F2200/492 , H03F2200/534 , H03F2200/75 , H03F2201/3218 , H03F2203/45036 , H03F2203/45101 , H03F2203/45112 , H03F2203/45134 , H03F2203/45136 , H03F2203/45138 , H03F2203/45146 , H03F2203/45151 , H03F2203/45156 , H03F2203/45168 , H03F2203/45172 , H03F2203/45208 , H03F2203/45256 , H03F2203/45292 , H03F2203/45312 , H03F2203/45356 , H03F2203/45374 , H03F2203/45386 , H03F2203/45402 , H03F2203/45436 , H03F2203/45544 , H03F2203/45596 , H03F2203/45622 , H04B2001/0408
摘要： A compensation circuit of a power amplifier includes a varactor, a voltage sensor and a control circuit. The varactor is coupled to an input terminal of the power amplifier. The voltage sensor is arranged for detecting an amplitude of an input signal of the power amplifier to generate a detecting result. The control circuit is coupled to the varactor and the voltage sensor, and is arranged for controlling a bias voltage of the varactor to adjust a capacitance of the varactor according to the detecting result.
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公开(公告)号：US20180019710A1
公开(公告)日：2018-01-18
申请号：US15342016
申请日：2016-11-02
发明人： Emre Ayranci , Miles Sanner
CPC分类号： H03F1/0277 , H03F1/086 , H03F1/565 , H03F3/193 , H03F3/195 , H03F3/72 , H03F2200/111 , H03F2200/18 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/243 , H03F2200/252 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/321 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/411 , H03F2200/42 , H03F2200/429 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/525 , H03F2200/61 , H03F2200/75 , H03F2203/7206 , H03F2203/7209 , H03F2203/7233
摘要： A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
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公开(公告)号：US09853615B2
公开(公告)日：2017-12-26
申请号：US15139030
申请日：2016-04-26
申请人： BROADCOM CORPORATION
发明人： Md Shakil Akter , Klaas Bult
CPC分类号： H03F3/45179 , H03F1/3211 , H03F1/34 , H03F3/45 , H03F3/45071 , H03F3/45085 , H03F3/45183 , H03F2200/294 , H03F2200/297 , H03F2200/372 , H03F2200/489 , H03G1/0029 , H03G1/0052 , H03G3/3015 , H03M1/0695 , H03M1/124 , H03M1/164
摘要： A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).
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公开(公告)号：US20170019075A1
公开(公告)日：2017-01-19
申请号：US15209816
申请日：2016-07-14
申请人： NXP B.V.
发明人： Gian Hoogzaad
CPC分类号： H03F1/52 , H03F3/195 , H03F3/45475 , H03F2200/18 , H03F2200/258 , H03F2200/294 , H03F2200/426 , H03F2200/441 , H03F2200/444 , H03F2200/451 , H03F2200/462 , H03F2200/481 , H03F2200/489 , H03F2200/492 , H03F2200/78
摘要： An RF amplifier comprising an input-transistor having an input-transistor-base terminal, an input-transistor-collector terminal and an input-transistor-emitter terminal; a degeneration-component connected between the input-transistor-emitter terminal and a ground terminal; and a protection-transistor having a protection-transistor-base terminal, a protection-transistor-collector terminal and a protection-transistor-emitter terminal. The input-transistor-base terminal is connected to the protection-transistor-emitter terminal, and the protection-transistor-base terminal is connected to the input-transistor-emitter.
摘要翻译： 一种RF放大器，包括具有输入晶体管基极端子的输入晶体管，输入晶体管集电极端子和输入晶体管 - 发射极端子; 连接在输入 - 晶体管 - 发射极端子和接地端子之间的退化分量; 以及具有保护晶体管基极端子的保护晶体管，保护晶体管集电极端子和保护晶体管 - 发射极端子。 输入晶体管基极端子连接到保护晶体管 - 发射极端子，保护晶体管基极端子连接到输入晶体管 - 发射极。
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公开(公告)号：US20150341007A1
公开(公告)日：2015-11-26
申请号：US14643854
申请日：2015-03-10
CPC分类号： H03G3/3036 , H03F1/223 , H03F3/19 , H03F3/193 , H03F3/68 , H03F2200/111 , H03F2200/294 , H03F2200/451 , H03F2200/489 , H03G1/0029 , H04B1/0053
摘要： An apparatus includes a first amplification stage configured to amplify a first carrier signal and a second amplification stage configured to amplify a second carrier signal. The first amplification stage is direct-current (DC) coupled to the second amplification stage. First circuitry is coupled to the first amplification stage and configured to control a first gain of the first amplification stage. The first circuitry includes a first gain control transistor configured to selectively divert a first bleed current from a first output of the first amplification stage. Second circuitry is coupled to the second amplification stage and configured to control a second gain of the second amplification stage independently of the first gain. The second circuitry includes a second gain control transistor configured to selectively divert a second bleed current from a second output of the second amplification stage.
摘要翻译： 一种装置包括被配置为放大第一载波信号的第一放大级和被配置为放大第二载波信号的第二放大级。 第一放大级是耦合到第二放大级的直流（DC）。 第一电路耦合到第一放大级并被配置为控制第一放大级的第一增益。 第一电路包括第一增益控制晶体管，其被配置为选择性地转移来自第一放大级的第一输出的第一泄放电流。 第二电路耦合到第二放大级并且被配置为独立于第一增益来控制第二放大级的第二增益。 第二电路包括第二增益控制晶体管，其被配置为选择性地转移来自第二放大级的第二输出的第二放电电流。
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