公开(公告)号：US20220374575A1

公开(公告)日：2022-11-24

申请号：US17748916

申请日：2022-05-19

Applicant: Lightmatter, Inc.

Inventor： Carl Ramey ,  Nicholas C. Harris ,  Hamid Eslampour

IPC: G06F30/38

Abstract: Electronic-photonic packages and related fabrication methods are described. A package may include a plurality of photonic integrated circuits (PICs), where each PIC comprises a photonic accelerator configured to perform matrix multiplication in the optical domain. The package may further include an application specific integrated circuit (ASIC) configured to control at least one of the photonic accelerators. The package further includes an interposer. The plurality of PICs are coupled to a first side of the interposer and the ASIC is coupled to a second side of the interposer opposite the first side. A first thermally conductive member in thermal contact with at least one of the PICs. The first thermally conductive member may include a heat spreader. A second thermally conductive member in thermal contact with the ASIC. The second thermally conductive member may include a lid. The first thermally conductive member faces the first side of the interposer, and the second thermally conductive member faces the second side of the interposer. In some embodiments, the interposer sits in part on a substrate and in part on the PICs.

公开(公告)号：US11455447B2

公开(公告)日：2022-09-27

申请号：US16321929

申请日：2017-07-31

Applicant: Siemens Industry Software Inc.

Inventor： Stephen Kenneth Sunter

IPC: G06F30/30 ,  G01R31/3183 ,  G06F30/3308 ,  G06F30/33 ,  G06F30/367 ,  G06F30/38

Abstract: Aspects of the disclosed technology relate to techniques of activity coverage assessment. Transistor-level circuit simulation is performed for a circuit design under a set of test stimuli, which determines values of one or more electrical properties for each of circuit elements of interest in the circuit design. The one or more electrical properties are selected based on information of the each of circuit elements of interest, which comprises what circuit element type the each of circuit elements of interest belongs to. Based on the values of the one or more electrical properties, activity coverage information comprising information about which circuit elements in the circuit elements of interest are active or inactive under the set of test stimuli is determined.

公开(公告)号：US11334702B1

公开(公告)日：2022-05-17

申请号：US17173963

申请日：2021-02-11

Applicant: Siemens Industry Software Inc.

Inventor： Kingshuk Banerjee ,  Roshan Lal ,  Anil Arora ,  Manjul Kishore Dudeja

IPC: G06F30/38 ,  G06F30/3308 ,  G06F30/398

Abstract: A computing system implementing a design verification system can elaborate a mixed-signal circuit design having a complex sandwich hierarchy using a standard digital solver and a standard analog solver, as opposed to a tightly coupled custom elaboration engine. The design verification system can parse the mixed-signal circuit design to identify analog design blocks and flatten the analog design blocks into the structural proxy blocks having parameter connections to digital design blocks in the mixed-signal circuit design. The design verification system can replace an analog portion of the mixed-signal circuit design with the structural proxy blocks and elaborate the structural proxy blocks and digital design blocks associated with a digital portion of the mixed-signal circuit design. The design verification system can elaborate the analog portion of the mixed-signal design and simulate the elaborated analog portion with an analog simulator and the elaborated digital portion with a digital simulator.

公开(公告)号：US11144697B1

公开(公告)日：2021-10-12

申请号：US17020868

申请日：2020-09-15

Applicant: RDC Semiconductor Co., Ltd.

Inventor： Hsin-Hsiung Yu ,  Ching-Chong Chuang ,  Chung-Ching Tseng

IPC: G06F30/367 ,  G06F30/38 ,  G06F30/3308 ,  H03K19/20 ,  H03K19/21

Abstract: A processing method for applying an analog dynamic circuit to a digital testing tool includes the following steps. In a step (a), a transistor-level analog dynamic circuit is provided. In a step (b), plural equivalent models are designed according to operations of plural transistors in the transistor-level analog dynamic circuit. In a step (c), a substitution operation is performed to substitute the equivalent models for dynamic logic elements in the transistor-level analog dynamic circuit. Consequently, a gate-level substitution circuit is produced. In a step (d), the gate-level substitution circuit is imported into a digital testing tool. Consequently, a test pattern is generated. In a step (e), the transistor-level analog dynamic circuit is tested according to the test pattern.

公开(公告)号：US20210312115A1

公开(公告)日：2021-10-07

申请号：US16836945

申请日：2020-04-01

Applicant: NXP USA, Inc.

Inventor： Sandeep Jain ,  Kirk Taylor ,  Vivek Sharma ,  Arpita Agarwal

IPC: G06F30/38 ,  G06F30/398 ,  G06F7/58 ,  G06F9/30

Abstract: A system to facilitate communication of a critical signal between functional circuitries of a system-on-chip utilizes a dynamic pattern to securely communicate the critical signal. The system includes selection and comparison circuits. The selection circuit is configured to select and output a set of dynamic pattern bits or a set of fixed reference bits, based on a logic state of the critical signal that is received from one functional circuitry. The comparison circuit is configured to output an output signal based on the set of dynamic pattern bits, and a set of intermediate bits that is derived from the set of dynamic pattern bits or the set of fixed reference bits. The output signal is provided to the other functional circuitry when a logic state of the output signal matches the logic state of the critical signal, thereby securely communicating the critical signal to the other functional circuitry.

公开(公告)号：US20210294954A1

公开(公告)日：2021-09-23

申请号：US16326603

申请日：2017-08-29

Applicant: NORTH CAROLINA STATE UNIVERSITY

Inventor： Behnam Kia ,  William Ditto ,  Yaman Dalal ,  Ravikanth Somsole ,  Siva Rama Maruthi Ven Donepudi Krishna Sesha Sai ,  Allen R. Mendes ,  Akshay Parnami ,  Robin George

IPC: G06F30/38 ,  G06F30/373 ,  G06F30/337 ,  G06F30/333

Abstract: A system can include a nonlinear circuit and a voltage decoder. The nonlinear circuit can perform an operation on an input voltage. The operation can be changed. A voltage decoder can be communicatively coupled to the nonlinear circuit for receiving an output voltage from the nonlinear circuit that results from the operation performed on the input voltage. The voltage decoder can compare the output voltage to a threshold voltage and determine a result of the operation.

公开(公告)号：US11017141B2

公开(公告)日：2021-05-25

申请号：US16874224

申请日：2020-05-14

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko Kalte ,  Dominik Lubeley ,  Marc Schlenger

IPC: G06F30/38 ,  G06F30/34 ,  G06F115/02 ,  G06F117/02

Abstract: A method for troubleshooting the program logic of a computer system. A first logic circuit and a first monitoring circuit, which is communicatively isolated from it, are programmed on a first programmable gate array of the computer system. A second logic circuit and a second monitoring circuit, which is communicatively isolated from it, are programmed on a second programmable gate array of the computer system. After an error has been detected in the program logic of the computer system, a first signal line, which applies a signal from the first logic circuit to a first signal input of the first monitoring circuit, is programmed in the first programmable gate array without changing the first logic circuit, and a second signal line, which applies a signal from the second logic circuit, is programmed in the second programmable gate array without changing the second logic circuit.

公开(公告)号：US11003825B1

公开(公告)日：2021-05-11

申请号：US16583643

申请日：2019-09-26

Applicant: Cadence Design Systems, Inc.

Inventor： Saleha Khatun ,  Sheng Qian ,  Wangyang Zhang ,  Elias Lee Fallon

IPC: G06F30/30 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F111/06

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design and determining an objective function associated with the electronic design. Embodiments may further include optimizing the objective function using Bayesian optimization and generating a best hyper-parameter setting based upon, at least in part, the Bayesian optimization.

公开(公告)号：US20200327271A1

公开(公告)日：2020-10-15

申请号：US16914009

申请日：2020-06-26

Applicant: Martin Langhammer ,  Dongdong Chen ,  Jason R. Bergendahl

Inventor： Martin Langhammer ,  Dongdong Chen ,  Jason R. Bergendahl

IPC: G06F30/34 ,  G06F30/38 ,  G06F9/30 ,  G06N20/00

Abstract: The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.