HYPERVISOR HIBERNATION
    52.
    发明申请

    公开(公告)号:US20240419475A1

    公开(公告)日:2024-12-19

    申请号:US18667648

    申请日:2024-05-17

    Applicant: Nutanix, Inc.

    Inventor: Binny Sher GILL

    Abstract: Upon receiving a request to hibernate a hypervisor of a virtualization system running on a first computer, acts are carried out to capture a state of the hypervisor, where the state of the hypervisor comprises hypervisor logical resource parameters and an execution state of the hypervisor. After hibernating the hypervisor by quiescing the hypervisor and storing the state of the hypervisor into a data structure, the data structure is moved to a different location. At a later moment in time, the data structure is loaded onto a second computing machine and restored. The restore operation restores the hypervisor and all of its state, including all of the virtual machines of the hypervisor as well as all of the virtual disks and other virtual devices of the virtual machines. Differences between the first computing machine and the second computing machine are reconciled before execution of the hypervisor on the second machine.

    Secure configuration of a virtual private network server

    公开(公告)号:US12170650B2

    公开(公告)日:2024-12-17

    申请号:US18239507

    申请日:2023-08-29

    Applicant: UAB 360 IT

    Abstract: A method including obtaining, by a virtual private network (VPN) server, an initial operating system from a memory associated with the VPN server; transmitting, by the VPN server while executing the initial operating system, a request to obtain a VPN operating system to enable the VPN server to provide VPN services; receiving, by the VPN server based at least in part on transmitting the request, the VPN operating system; and executing, by the VPN server, the VPN operating system to provide the VPN services based at least in part on storing the VPN operating system on a volatile memory associated with the VPN server is disclosed. Various other aspects are contemplated.

    System with dynamically selectable firmware image sequencing for production test, debug, prototyping

    公开(公告)号:US12169720B2

    公开(公告)日:2024-12-17

    申请号:US17957708

    申请日:2022-09-30

    Abstract: A system has a memory programmed with multiple firmware images each having an associated distinct entry point, a processor, a writable hardware register, and a controller external to the processor that, prior to each reset of a sequence of resets of the processor, reads the entry point of a firmware image from the hardware register and causes the processor to begin fetching instructions at the entry point read from the hardware register. The firmware images include boot, mission mode, and at least one other firmware image. The memory may be writeable with a modifiable version of a post-production mission mode, debug, prototype, or patched ROM firmware image. A second controller writes a second entry point to the hardware register prior to an initial reset such that the external controller reads the second entry point and causes fetching instructions at the second entry point rather than the initial entry point.

    MEMORY-PARTITION-BASED DEVICE-STARTUP METHOD AND APPARATUS, AND ELECTRONIC DEVICE

    公开(公告)号:US20240411564A1

    公开(公告)日:2024-12-12

    申请号:US18633014

    申请日:2024-04-11

    Abstract: Disclosed are a memory-partition-based device-startup method and apparatus, a computer readable storage medium, and an electronic device. The method includes: determining a boot status of an electronic device in a first boot mode at a preset occasion; reading, based on the boot status, first boot information from a first partition of a target memory; booting the electronic device in a second boot mode based on the first boot information, and acquiring system update information for the electronic device from a system update server; updating, based on the system update information, second boot information in a second partition of the target memory; and booting the electronic device in the first boot mode based on the updated second boot information.

    METHOD TO RESET CONFIGURABLE UNITS IN A RECONFIGURABLE PROCESSOR

    公开(公告)号:US20240385929A1

    公开(公告)日:2024-11-21

    申请号:US18788391

    申请日:2024-07-30

    Inventor: Manish K. SHAH

    Abstract: Disclosed is a method for resetting configurable units in a reconfigurable processor with an array of configurable units and a force-quit controller on an integrated circuit substrate. The array includes multiple sub-arrays of configurable units. The method involves receiving a force-quit command at the force-quit controller and generating force-quit control signals to reset configurable units in a specific sub-array of the plurality of sub-arrays. The specific sub-array contains the force-quit controller. This method enhances the efficiency and reliability of reconfigurable processors by enabling targeted and controlled resets of configurable units within the reconfigurable processor architecture.

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