公开(公告)号：US06121079A

公开(公告)日：2000-09-19

申请号：US104561

申请日：1998-06-25

Applicant: Jae Kap Kim

Inventor： Jae Kap Kim

IPC: H01L27/10 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/44

CPC classification number: G11C11/405 ,  H01L27/108 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/908

Abstract: In DRAM comprising a read pass transistor, a write pass transistor and a storage transistor, a depletion transistor is connected to a source of the storage transistor. On a part of the source and drain of the depletion transistor, by forming an impurity region of same conductivity as that of the substrate on which the transistors are formed, a substrate voltage applied to the substrate is supplied to the storage transistor through the depletion transistor. An additional metal wire for connecting the source of the storage transistor to Vss voltage(ground voltage or substrate voltage)terminal and a contact hole area for such metal wire are not required. Accordingly, a high integration of the semiconductor can be accomplished and a a reduction of reliability thereof can be decreased.

Abstract translation: 在包括读传输晶体管，写通晶体管和存储晶体管的DRAM中，耗尽晶体管连接到存储晶体管的源极。 在耗尽晶体管的源极和漏极的一部分上，通过形成与其上形成晶体管的衬底相同导电性的杂质区，施加到衬底的衬底电压通过耗尽晶体管提供给存储晶体管 。 不需要用于将存储晶体管的源极连接到Vss电压（接地电压或衬底电压）端子的附加金属线和用于这种金属线的接触孔区域。 因此，可以实现半导体的高集成度，并且可以降低其可靠性。

公开(公告)号：US5963497A

公开(公告)日：1999-10-05

申请号：US080813

申请日：1998-05-18

Applicant: Wayland Bart Holland

Inventor： Wayland Bart Holland

IPC: G11C11/405 ,  G11C11/406 ,  G11C7/00

CPC classification number: G11C11/406

Abstract: A memory 200 including an array 201 of rows and columns of 2-transistor, 1-capacitor memory cells 301 of the cells of each row coupled to first and second wordlines 303a, 303b and the cells of each column coupled to a pair of bitlines 302a, 302b. Refresh circuitry 208 activates the first wordline 303a plus selected said row and refreshes the cells 301 of that row through a first one of the bitlines 302a of each of the columns. Data access circuitry 202, 204 substantially simultaneously activates the second said wordline 303b of a second selected row and accesses selected cells of the second row through a second one of the bitlines 302b in the corresponding columns.

Abstract translation: 存储器200，其包括耦合到第一和第二字线303a，303b的每行的单元的单元的2-晶体管，1-电容器存储单元301的行和列的阵列201以及耦合到一对位线302a的每列的单元 ，302b。 刷新电路208激活第一字线303a加上所选择的行，并且通过列中的每一列的位线302a中的第一位刷新该行的单元301。 数据访问电路202,204基本上同时激活第二选定行的第二所述字线303b，并且通过相应列中的位线302b中的第二行访问第二行的选定单元。

公开(公告)号：US5943270A

公开(公告)日：1999-08-24

申请号：US979501

申请日：1997-11-26

Applicant: Shekhar Yeshwant Borkar

Inventor： Shekhar Yeshwant Borkar

IPC: G11C11/403 ,  G11C11/404 ,  G11C11/405 ,  G11C16/04

CPC classification number: G11C11/404 ,  G11C11/403 ,  G11C11/405

Abstract: A DRAM cell is provided which includes a read bit line capable of being precharged to a first voltage level, a write bit line capable of carrying data, a read word line capable of being asserted at a second voltage level, and a write word line capable of being asserted at about the first voltage level. A first switching device having an enable input is coupled between the read bit line and the word read line. A second switching device having an enable input coupled to the write word line is coupled between the write bit line and the enable input of the first switching device.

Abstract translation: 提供了一种DRAM单元，其包括能够预充电到第一电压电平的读位线，能够承载数据的写位线，能够以第二电压电平被断言的读字线和能够写入的字线 在大约第一电压电平被断言。 具有使能输入的第一开关器件耦合在读位线和字读线之间。 具有耦合到写字线的使能输入的第二开关器件耦合在第一开关器件的写入位线和使能输入端之间。

公开(公告)号：US5818776A

公开(公告)日：1998-10-06

申请号：US838287

申请日：1997-04-17

Applicant: Koji Shibutani ,  Hideshi Maeno

Inventor： Koji Shibutani ,  Hideshi Maeno

IPC: G11C7/00 ,  G11C11/00 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409

CPC classification number: G11C11/405 ,  G11C11/005 ,  G11C11/408 ,  G11C11/409

Abstract: When stored data of a plurality of memory cells (MC00 to MC03, MC10 to MC13, MC20 to MC23, MC30 to MC33) arranged in a matrix are sequentially read out, a reading access control circuit (101) outputs a row address and a column address to a row decoder (102) and a reading bit-line selector (103), respectively, for an access to the memory cells. The reading access control circuit (101) outputs the row address and the column address so that an n-type memory cell may be first selected by the reading bit-line selector (103) after activation of the selected reading word line every time one of the reading word lines (RWL0 to RWL3) is selected by the row decoder (102). With this configuration, data can be sequentially read out at higher speed from a plurality of memory cells arranged in a matrix.

Abstract translation: 读取访问控制电路（101）当按矩阵排列的多个存储单元（MC00〜MC03，MC10〜MC13，MC20〜MC23，MC30〜MC33）的数据被顺序地读出时，输出行地址和列 分别用于访问存储器单元的行解码器（102）和读取位线选择器（103）的地址。 读取访问控制电路（101）输出行地址和列地址，使得在每次选择的读取字线激活之后，读取位线选择器（103）可以首先选择n型存储单元 读取字线（RWL0〜RWL3）由行解码器（102）选择。 利用这种配置，可以从布置在矩阵中的多个存储单元中以更高的速度顺序读出数据。

公开(公告)号：US5712817A

公开(公告)日：1998-01-27

申请号：US648755

申请日：1996-05-16

Applicant: Jung Won Suh

Inventor： Jung Won Suh

IPC: H01L21/8247 ,  G11C11/401 ,  G11C11/403 ,  G11C11/405 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC classification number: H01L27/108 ,  G11C11/403 ,  G11C11/405

Abstract: The present invention provides a DRAM cell comprising: an input/output bit line; a first word line being activated by a write control signal; a second word line being activated by a read control signal; a first transistor having a first terminal coupled to said input/output bit line, a second terminal, and having a gate electrode coupled to said first word line for coupling said first terminal to said second terminal responsive to said write control signal; and a second transistor having a gate electrode coupled to said second word line, a first terminal coupled to a reference voltage terminal, a second terminal coupled to said input/output bit line, and having a floating gate electrode coupled to said second terminal of said first transistor for coupling said first terminal to said second terminal responsive to said read control signal, wherein the voltage level of said input/output bit line is transferred to said floating gate, and wherein said first transistor varies the threshold voltage of said second transistor at a write operation and is turned off at a read operation, and said second transistor transfers the voltage level of said reference voltage terminal to said input/output bit line at said read operation and is turned off at said write operation.

Abstract translation: 本发明提供了一种DRAM单元，包括：输入/输出位线; 第一字线被写入控制信号激活; 第二字线被读取控制信号激活; 第一晶体管，其具有耦合到所述输入/输出位线的第一端子，第二端子，并且具有耦合到所述第一字线的栅电极，用于响应于所述写入控制信号将所述第一端子耦合到所述第二端子; 以及第二晶体管，其具有耦合到所述第二字线的栅极电极，耦合到参考电压端子的第一端子，耦合到所述输入/输出位线的第二端子，并且具有耦合到所述第二字线的所述第二端子的浮置栅电极 第一晶体管，用于响应于所述读取控制信号将所述第一端子耦合到所述第二端子，其中所述输入/输出位线的电压电平被传送到所述浮置栅极，并且其中所述第一晶体管改变所述第二晶体管的阈值电压 写操作并在读取操作时被关闭，并且所述第二晶体管在所述读取操作时将所述参考电压端子的电压电平传送到所述输入/输出位线，并且在所述写入操作时将其截止。

公开(公告)号：US5657267A

公开(公告)日：1997-08-12

申请号：US540604

申请日：1995-10-05

Applicant: Mark W. Levi

Inventor： Mark W. Levi

IPC: G11C5/00 ,  G11C11/405 ,  G11C11/24

CPC classification number: G11C5/005 ,  G11C11/405

Abstract: Individual cells in a memory array are structured and interconnected to permit detection and identification of the locations of errors known as Single Event Upsets (SEUs), with the correction and identification of an affected cell made using only a single parity bit for a group of cells in a memory array, eliminating the necessity for reading an entire memory in order to detect SEUs immediately, and eliminate large numbers of non-useful correction-code cells in order to increase the net useful density of cells in a memory and tolerate a larger rate of SEU events than for previous methods, additionally eliminate the need for purification of packaging materials for memory arrays by removing most radioactive materials and providing a further economic benefit by eliminating the need for organic coatings, which can cause reliability hazards, and to block alpha particles originating in packaging.

Abstract translation: 存储器阵列中的单个单元被构造和互连以允许检测和识别被称为单事件颠簸（SEU）的错误的位置，其中对于一组单元仅使用单个奇偶校验位进行修改和识别 在存储器阵列中，消除了读取整个存储器以便立即检测SEU的必要性，并且消除大量无用的校正码单元，以便增加存储器中的单元的净有用密度并且容忍更大的速率 的SEU事件比以前的方法，另外消除了通过去除大多数放射性材料并且通过消除对可能导致可靠性危害的有机涂层的需要并且阻止α粒子来提供另外的经济效益来净化记忆阵列的包装材料的需要 源于包装。

公开(公告)号：US5654912A

公开(公告)日：1997-08-05

申请号：US568500

申请日：1995-12-07

Applicant: Takehiro Hasegawa ,  Yukihito Oowaki ,  Hitoshi Kuyama

Inventor： Takehiro Hasegawa ,  Yukihito Oowaki ,  Hitoshi Kuyama

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/24

CPC classification number: G11C11/4096 ,  G11C11/4045 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/103

Abstract: A semiconductor memory device comprises a memory array in which word lines are driven by a single decoder or a plurality of memory arrays driven by a plurality of decoders operating with the same row address, in the memory array or memory arrays memory cell units in which a plurality of memory cells are connected in series being arranged in the form of an array, a plurality of sense amplifier arrays constituted by arranging a plurality of sense amplifiers each provided for a pair of bit lines or a plurality of pairs of bit lines to read out data from the memory cells of the memory cell arrays, the sense amplifier arrays being divided into a plurality of blocks, and the blocks corresponding to one memory cell array, a register array having a plurality of registers for storing data read out by the plurality of sense amplifiers, the register array being divided into a plurality of blocks, and the blocks corresponding to the sense amplifier block and one memory cell array, and a control circuit for independently controlling the blocks of the sense amplifier arrays and the register array and independently reading out data from the registers in the blocks.

Abstract translation: 半导体存储器件包括存储器阵列，其中字线由单个解码器驱动，或者由存储器阵列或存储器阵列存储单元单元中的由相同行地址操作的多个解码器驱动的多个存储器阵列驱动，其中， 多个存储单元以阵列的形式串联连接，多个读出放大器阵列通过布置多个读出放大器而构成，每个读出放大器分别设置用于一对位线或多对位线以读出 来自存储单元阵列的存储单元的数据，读出放大器阵列被划分为多个块，以及对应于一个存储单元阵列的块，具有多个寄存器的寄存器阵列，用于存储由多个块读出的数据 读出放大器，寄存器阵列被分成多个块，以及对应于读出放大器块和一个存储单元阵列的块，以及控制ci 用于独立控制读出放大器阵列和寄存器阵列的块，并独立地从块中的寄存器读出数据。

公开(公告)号：US5652728A

公开(公告)日：1997-07-29

申请号：US524930

申请日：1995-09-08

Applicant: Shiro Hosotani ,  Minobu Yazawa ,  Kazuya Yamanaka

Inventor： Shiro Hosotani ,  Minobu Yazawa ,  Kazuya Yamanaka

IPC: G11C11/405 ,  G11C7/00 ,  G11C11/401 ,  G11C11/4099

CPC classification number: G11C11/4099

Abstract: Dummy information of a third level, which is between first and second levels written in a plurality of memory cells, is written in a dummy memory cell from a source node through transistors. Thus, a potential difference is caused between a read bit line and a dummy read bit line in reading. A potential comparison circuit indicates the level of information read from any memory cell on the basis of the comparison result as to the potentials of the dummy read bit line and the read bit line. Thus, the read rate is increased, the read operation is stabilized and increase of the chip area is suppressed.

Abstract translation: 写入多个存储单元的第一级和第二级之间的第三级的虚拟信息通过晶体管从源节点写入虚拟存储单元。 因此，读取中的读取位线和虚拟读取位线之间产生电位差。 潜在的比较电路根据关于虚拟读取位线和读取位线的电位的比较结果来指示从任何存储器单元读取的信息的电平。 因此，读取速率增加，读取操作稳定，并且抑制了芯片面积的增加。

公开(公告)号：US5646903A

公开(公告)日：1997-07-08

申请号：US611895

申请日：1996-03-06

Applicant: R. Anders Johnson

Inventor： R. Anders Johnson

IPC: G11C8/16 ,  G11C11/405 ,  G11C11/40

CPC classification number: G11C11/405 ,  G11C8/16

Abstract: A DRAM memory having shared read/write lines. The DRAM memory is comprised of an array of 3T memory cells. Data is digitally stored in the form of capacitors that are either charged or discharged. Horizontal data lines are used to convey data bits to be stored in the array of memory cells. Vertical read/write lines are used to perform both read and write functions. Activating a single read/write line causes a bit of data from a memory cell to be placed onto a corresponding data line. Simultaneously, an inverted copy of that data bit is stored in an adjacent memory cell. Hence, instead of having a separate read line and a separate word line for each memory cell, the present invention has a dual function read/write word line.

Abstract translation: 具有共享读/写线的DRAM存储器。 DRAM存储器由3T存储器单元阵列组成。 数据以电容器的形式进行数字存储，这些电容器被充电或放电。 水平数据线用于传送要存储在存储单元阵列中的数据位。 垂直读/写行用于执行读写功能。 激活单个读/写行将导致来自存储器单元的数据位被放置在相应的数据行上。 同时，该数据位的反转副本被存储在相邻的存储单元中。 因此，本发明不具有用于每个存储单元的单独的读取行和单独的字线，而是具有双功能读/写字线。

公开(公告)号：US5537347A

公开(公告)日：1996-07-16

申请号：US297957

申请日：1994-08-31

Applicant: Shinichiro Shiratake ,  Daisaburo Takashima

Inventor： Shinichiro Shiratake ,  Daisaburo Takashima

IPC: G11C11/401 ,  G11C11/404 ,  G11C11/405 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C11/404 ,  H01L27/108

Abstract: A NAND-type dynamic semiconductor memory device having a folded bit architecture which reduces chip size and decreases array noise and soft error. The device is comprised of a plurality of memory cell groups, each group comprised of a plurality of bit memory cells connected in series, each bit memory cell having a MOS transistor and a capacitor. Two adjacent memory cell groups are connected respectively to one of a pair of bit lines. Each bit line is coupled respectively to a first one of the transistors located at the end of each memory cell group. A pair of first word lines are coupled respectively to the gates of the first one of the transistors coupled to the paired bit lines. A plurality of second word lines are each commonly coupled to the gates of corresponding ones of the transistors of the memory cell groups coupled to the paired bit lines.

Abstract translation: 具有折叠位架构的NAND型动态半导体存储器件，其减小了芯片尺寸并降低了阵列噪声和软错误。 该装置由多个存储单元组组成，每组包括串联连接的多个位存储单元，每个位存储单元具有MOS晶体管和电容器。 两个相邻的存储单元组分别连接到一对位线之一。 每个位线分别耦合到位于每个存储单元组末端的第一个晶体管。 一对第一字线分别耦合到耦合到成对位线的晶体管的第一个的栅极。 多个第二字线各自共同耦合到耦合到成对位线的存储单元组的相应晶体管的栅极。