公开(公告)号：US5193018A

公开(公告)日：1993-03-09

申请号：US783575

申请日：1991-10-28

Applicant: Biing-Seng Wu

Inventor： Biing-Seng Wu

IPC: G02F1/13

CPC classification number: G02F1/13

Abstract: A matrix display system includes an active matrix display device having an array of liquid crystal picture elements (pixel) with associated switches using thin film transistors (TFT). The pixels are arranged in groups, each having two pixels and switched by two complementary TFTs. The n-channel TFTs are switched on by a positive pulse and the p-channel TFTs are switched on by a negative pulse. The two switching signals are alternately fed from a row conductor which feeds both the n-channel TFTs and the p-channel TFTs on the same row. Each group of the two TFTs are addressed via the same row conductor and the same column conductor, which carries the data signal. In this way, either the number of row conductors are reduced by one half or the number of column conductors are reduced by one half.

Abstract translation: 矩阵显示系统包括具有使用薄膜晶体管（TFT）的相关开关的液晶像素（像素）阵列的有源矩阵显示装置。 像素被分组布置，每个具有两个像素并由两个互补TFT切换。 n沟道TFT由正脉冲接通，p沟道TFT通过负脉冲接通。 两个开关信号从在同一行馈送n沟道TFT和p沟道TFT两者的行导体交替馈送。 两组TFT中的每一组通过同一行导体和同一列导体进行寻址，该列导体承载数据信号。 以这种方式，行导体的数量减少了一半，或者列导体的数量减少了一半。

公开(公告)号：US5017983A

公开(公告)日：1991-05-21

申请号：US389227

申请日：1989-08-03

Applicant: Biing-Seng Wu

Inventor： Biing-Seng Wu

IPC: H01L21/336 ,  H01L29/786

CPC classification number: H01L29/6675 ,  H01L29/78645 ,  H01L29/78648

Abstract: The present invention is a high speed thin film transistor with an accumulation gate and a depletion gate. When a positive voltage is applied to the accumulation gate, the electrons are accumulated in the channel region of the accumulation gate and the transistor is operated at the "on" state. If a negative voltage is applied to the depletion gate, the accumulated electrons are depleted, and the transistor is operated at the "off" state. The on-current of the thin film transistor is the same as that of conventional thin film transistors; however, a smaller off-current of the transistor is obtained.

Abstract translation: 本发明是具有堆积栅极和耗尽栅极的高速薄膜晶体管。 当向积聚栅极施加正电压时，电子被累积在积聚栅极的沟道区域中，并且晶体管在“导通”状态下操作。 如果向耗尽栅施加负电压，则累积的电子被耗尽，并且晶体管在“关”状态下运行。 薄膜晶体管的导通电流与传统薄膜晶体管的导通电流相同; 然而，获得晶体管的较小的截止电流。