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公开(公告)号：US20110240944A1
公开(公告)日：2011-10-06
申请号：US13159594
申请日：2011-06-14
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1608 , H01L45/1683 , H01L45/1691
摘要： A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell.
摘要翻译： 一种用于制造包括存储单元的相变存储器件的方法包括将通孔图案化成与要连接到存取电路的导电触头阵列相对应的衬底的接触表面，将每个通孔用保形导电晶种层 形成覆盖导电种子层的电介质层，并将每个通孔的中心区域蚀刻到接触表面，以在接触表面露出共形导电种子层。 该方法还包括在保形导电晶种层的暴露部分上电镀相变材料，使形成导电材料的中心区域内的相变材料凹陷在凹陷相变材料上，该导电材料在凹陷相变材料上保持导电，保形导电 晶种层沿每个通孔的侧面形成，并且在每个存储单元上形成顶部电极。
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公开(公告)号：US07910911B2
公开(公告)日：2011-03-22
申请号：US12511602
申请日：2009-07-29
IPC分类号： H01L47/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： An embodiment of the present invention includes a phase change memory (PCM) structure configurable for use as a nonvolatile storage element. The element includes at least one bottom electrode; at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; and at least one heater layer on at least a portion of an upper surface of the phase change material layer, wherein the heater layer has a tapered shape such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.
摘要翻译： 本发明的实施例包括可配置为用作非易失性存储元件的相变存储器（PCM）结构。 该元件包括至少一个底部电极; 在所述底部电极的上表面的至少一部分上的至少一个相变材料层; 以及在所述相变材料层的上表面的至少一部分上的至少一个加热层，其中所述加热器层具有锥形形状，使得所述加热器层的上表面的横截面宽度比 加热器层的底表面的与相变材料层接触的横截面宽度。
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公开(公告)号：US20090189139A1
公开(公告)日：2009-07-30
申请号：US12021577
申请日：2008-01-29
IPC分类号： H01L45/00
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/165 , H01L45/1666
摘要： A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.
摘要翻译： 提供一种制造电极的方法，其包括在电介质层的导电结构的顶部设置第一相变材料的柱; 或倒置结构; 在电介质层的上方形成绝缘材料，并邻近所述柱，其中所述第一绝缘材料的上表面与所述柱的上表面共面; 将所述柱的上表面凹陷在所述绝缘材料的上表面下方以提供凹腔; 以及在所述凹腔和所述绝缘材料的上表面之上形成第二相变材料，其中所述第二相变材料具有比所述第一相变材料更大的相电阻率。
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64.发明申请公开(公告)号：US20090186443A1
公开(公告)日：2009-07-23
申请号：US12017848
申请日：2008-01-22
申请人： Eric A. Joseph , Chung Hon Lam , Gerhard I. Meijer , Stephen M. Rossnagel , Alejandro Gabriel Schrott
发明人： Eric A. Joseph , Chung Hon Lam , Gerhard I. Meijer , Stephen M. Rossnagel , Alejandro Gabriel Schrott
IPC分类号： H01L21/34
CPC分类号： H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/1273 , H01L45/147 , H01L45/16
摘要： A method of incorporating oxygen vacancies near an electrode/oxide interface region of a complex metal oxide programmable memory cell which includes forming a first electrode of a metallic material which remains metallic upon oxidation, forming a second electrode facing the first electrode, forming an oxide layer in between the first and second electrodes, applying an electrical signal to the first electrode such that oxygen ions from the oxide layer are embedded in and oxidize the first electrode, and forming oxygen vacancies near the electrode/oxide interface region of the complex metal oxide programmable memory cell.
摘要翻译： 一种在复合金属氧化物可编程存储单元的电极/氧化物界面区域附近引入氧空位的方法，其包括在氧化时形成保持金属的金属材料的第一电极，形成面向第一电极的第二电极，形成氧化物层 在第一和第二电极之间，向第一电极施加电信号，使得来自氧化物层的氧离子嵌入并氧化第一电极，并在复合金属氧化物可编程的电极/氧化物界面区域附近形成氧空位 记忆单元
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65.发明申请METHOD AND APPARATUS FOR FABRICATING SUB-LITHOGRAPHY DATA TRACKS FOR USE IN MAGNETIC SHIFT REGISTER MEMORY DEVICES 有权用于制作用于磁移位置存储器件的次数据轨迹的方法和装置公开(公告)号：US20090046493A1
公开(公告)日：2009-02-19
申请号：US11838663
申请日：2007-08-14
申请人： SOLOMON ASSEFA , Michael C. Gaidis , Eric A. Joseph , Stuart Stephen Papworth Parkin , Christy S. Tyberg
发明人： SOLOMON ASSEFA , Michael C. Gaidis , Eric A. Joseph , Stuart Stephen Papworth Parkin , Christy S. Tyberg
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C19/0808 , H01L21/76816 , H01L43/08
摘要： In one embodiment, the invention is a method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices. One embodiment of a memory device includes a first stack of dielectric material formed of a first dielectric material, a second stack of dielectric material surrounding the first stack of dielectric material and formed of at least a second dielectric material, and at least one data track for storing information, positioned between the first stack of dielectric material and the second stack of dielectric material, the data track having a high aspect ratio and a substantially rectangular cross section.
摘要翻译： 在一个实施例中，本发明是用于制造用于磁移位寄存器存储器件的子光刻数据磁道的方法和装置。 存储器件的一个实施例包括由第一电介质材料形成的介电材料的第一叠层，围绕第一电介质材料堆叠并由至少第二电介质材料形成的第二电介质材料叠层，以及至少一个用于 存储位于所述第一电介质材料堆叠和所述第二电介质材料堆之间的信息，所述数据轨道具有高纵横比和基本上矩形的横截面。
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66.发明授权公开(公告)号：US06624068B2
公开(公告)日：2003-09-23
申请号：US09939259
申请日：2001-08-24
IPC分类号： H01L21302
CPC分类号： H01L21/0276 , H01L21/32137 , H01L21/32139
摘要： A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an anti-reflective coating (ARC) comprising two layers having matched indices of refraction (n) and extinction coefficient (k) selected to reduce reflection to less than 1% with 193 nm wavelength exposure. The ARC is subsequently patterned to serve as an etch hardmask. Preferably the ARC mask consists of a first layer of between 300 and 1500 angstroms of silicon rich silicon nitride having an extinction coefficient of from 0.77 to 1.07, and a second layer of between 170 and 320 angstroms of silicon oxynitride having an extinction coefficient of about 0.32.
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67.发明授权High aspect ratio and reduced undercut trench etch process for a semiconductor substrate 有权用于半导体衬底的高纵横比和减少的底切沟槽蚀刻工艺公开(公告)号：US08652969B2
公开(公告)日：2014-02-18
申请号：US13281715
申请日：2011-10-26
IPC分类号： H01L21/768 , H01L23/00
CPC分类号： H01L29/0657 , H01L21/30655 , H01L21/76898
摘要： A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved.
摘要翻译： 在各向异性蚀刻工艺中使用氢氟烃气体作为聚合物沉积气体，其使用蚀刻剂气体和聚合物沉积气体的交替来蚀刻半导体衬底中的深沟槽。 氢氟烃气体可以在半导体衬底的顶表面上与聚合物的厚度一致的厚度在沟槽的侧壁上产生厚的富碳和含氢聚合物。 厚的富碳和含氢聚合物保护沟槽的侧壁，从而使硬掩模下方的底切最小化，而不降低整体速率。 在一些实施例中，可以实现整体蚀刻速率的改进。
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公开(公告)号：US20130001500A1
公开(公告)日：2013-01-03
申请号：US13612552
申请日：2012-09-12
IPC分类号： H01L45/00
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/165 , H01L45/1666
摘要： A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.
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69.发明申请公开(公告)号：US20120299136A1
公开(公告)日：2012-11-29
申请号：US13568670
申请日：2012-08-07
IPC分类号： H01L29/82
CPC分类号： H01L43/12 , H01L27/222 , H01L43/08
摘要： A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.
摘要翻译： 半导体器件包括包括M2图案化区域的衬底。 在M2图案化区域上形成VA柱结构。 VA柱结构包括一个减少图案化的金属层。 VA柱结构是亚光刻接触。 在氧化物层和VA柱的金属层上形成MTJ堆叠。 MTJ叠层的尺寸和MTJ叠层的形状各向异性独立于亚光刻触点的尺寸和形状各向异性。
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70.发明授权Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process 有权用于形成PCRAM和自对准回蚀工艺的自对准位线的方法公开(公告)号：US08273598B2
公开(公告)日：2012-09-25
申请号：US13020051
申请日：2011-02-03
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译： 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。
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