公开(公告)号：US08476763B2

公开(公告)日：2013-07-02

申请号：US13237514

申请日：2011-09-20

Applicant: Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

Inventor： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC: H01L23/48 ,  H01L21/4763 ,  H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  G06F17/50

CPC classification number: H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

Abstract translation: 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US20130012023A1

公开(公告)日：2013-01-10

申请号：US13533653

申请日：2012-06-26

Applicant: In-sun Park ,  Gil-heyun Choi ,  Ji-soon Park ,  Jong-myeong Lee ,  Jong-won Hong ,  Hei-seung Kim

Inventor： In-sun Park ,  Gil-heyun Choi ,  Ji-soon Park ,  Jong-myeong Lee ,  Jong-won Hong ,  Hei-seung Kim

IPC: H01L21/308

CPC classification number: H01L23/48 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76816 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/06 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.

Abstract translation: 根据示例性实施例，形成微图案的方法包括在衬底的虚拟区域上形成具有第一宽度的虚拟图案，并且在衬底的有源线区域上形成具有第二宽度的单元图案。 有源线区域可以与虚拟区域相邻，并且第二宽度可以小于第一宽度。 该方法可以进一步包括通过在有源线区域和虚拟区域上形成种子层来形成镶嵌金属化，在基片的整个表面上形成导电材料层，并平坦化导电材料层以形成金属线。

公开(公告)号：US20120193792A1

公开(公告)日：2012-08-02

申请号：US13237514

申请日：2011-09-20

Applicant: Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

Inventor： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

Abstract translation: 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US08192592B2

公开(公告)日：2012-06-05

申请号：US12051043

申请日：2008-03-19

Applicant: Do-Hyung Kim ,  Shin-Jae Kang ,  In-Sun Park ,  Hyun-Seok Lim ,  Gyu-Hwan Oh

Inventor： Do-Hyung Kim ,  Shin-Jae Kang ,  In-Sun Park ,  Hyun-Seok Lim ,  Gyu-Hwan Oh

IPC: C23C14/04

CPC classification number: C23C14/3414 ,  C23C14/0623 ,  G11B7/2433 ,  G11B7/252 ,  G11B2007/24312 ,  G11B2007/24314 ,  G11B2007/24316 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

Abstract: The present invention provides methods of forming a phase-change material layer including providing a substrate and a chalcogenide target including germanium (Ge), antimony (Sb) and tellurium (Te) at a temperature wherein tellurium is volatilized and antimony is not volatilized, and performing a sputtering process to form the phase-change material layer including a chalcogenide material on the substrate. Methods of manufacturing a phase-change memory device using the same are also provided.

Abstract translation: 本发明提供了形成相变材料层的方法，包括在碲被挥发并且锑不挥发的温度下提供包括锗（Ge），锑（Sb）和碲（Te）的基板和硫族化物靶，以及 进行溅射工艺以在衬底上形成包括硫族化物材料的相变材料层。 还提供了制造使用其的相变存储器件的方法。

公开(公告)号：US20110315225A1

公开(公告)日：2011-12-29

申请号：US13166435

申请日：2011-06-22

Applicant: Yeong Suk Choi ,  Soo-Ghang Ihn ,  Bulliard Xavier ,  Sung Young Yun ,  Youn Hee Lim ,  In Sun Park ,  Yeon Ji Chung

Inventor： Yeong Suk Choi ,  Soo-Ghang Ihn ,  Bulliard Xavier ,  Sung Young Yun ,  Youn Hee Lim ,  In Sun Park ,  Yeon Ji Chung

IPC: C08G75/06 ,  H01L51/46

CPC classification number: H01L51/0043 ,  B82Y10/00 ,  C08G61/126 ,  C08G2261/124 ,  C08G2261/142 ,  C08G2261/1424 ,  C08G2261/1426 ,  C08G2261/1428 ,  C08G2261/146 ,  C08G2261/148 ,  C08G2261/3243 ,  C08G2261/414 ,  C08G2261/91 ,  C09B69/109 ,  H01L51/0003 ,  H01L51/0036 ,  H01L51/0047 ,  H01L51/4253 ,  Y02E10/549

Abstract: An electron-donating polymer including a repeating unit A with a repeating unit represented by Chemical Formula 1 and at least one of repeating units represented by Chemical Formulae 2-4.

Abstract translation: 含有由化学式1表示的重复单元的重复单元A和由化学式2-4表示的重复单元中的至少一种的给电子聚合物。

公开(公告)号：US20100243982A1

公开(公告)日：2010-09-30

申请号：US12796084

申请日：2010-06-08

Applicant: Gyu-Hwan Oh ,  Shin-Jae Kang ,  In-Sun Park ,  Hyun-Seok Lim ,  Nak-Hyun Lim ,  Hyun-Suk Lee

Inventor： Gyu-Hwan Oh ,  Shin-Jae Kang ,  In-Sun Park ,  Hyun-Seok Lim ,  Nak-Hyun Lim ,  Hyun-Suk Lee

IPC: H01L45/00

CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

Abstract: Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming an ohmic layer on an upper surface of a conductive structure and extending away from the structure along at least a portion of a sidewall of an opening in an insulation layer. An electrode layer is formed on the ohmic layer. A variable resistivity material is formed on the insulation layer and electrically connected to the electrode layer.

Abstract translation: 公开了制造集成电路存储单元和集成电路存储单元的方法。 可以通过在导电结构的上表面上形成欧姆层并沿着绝缘层中的开口的侧壁的至少一部分远离结构延伸来制造集成电路存储单元。 在欧姆层上形成电极层。 在绝缘层上形成可变电阻率材料并与电极层电连接。

公开(公告)号：US07524724B2

公开(公告)日：2009-04-28

申请号：US11173771

申请日：2005-06-30

Applicant: Rak-Hwan Kim ,  Hyun-Seok Lim ,  Young-Joo Cho ,  In-Sun Park ,  Hyeon-Deok Lee ,  Hyun-Suk Lee

Inventor： Rak-Hwan Kim ,  Hyun-Seok Lim ,  Young-Joo Cho ,  In-Sun Park ,  Hyeon-Deok Lee ,  Hyun-Suk Lee

IPC: H01L21/20

CPC classification number: C23C16/45529 ,  C23C16/34 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91

Abstract: A method of fabricating a storage capacitor includes depositing a first titanium nitride layer on a dielectric layer using a chemical vapor deposition technique or an atomic layer deposition technique performed at a first temperature with reactant gases of titanium chloride (TiCl4) gas and ammonia (NH3) gas at a predetermined flow ratio and depositing a second titanium nitride layer on the first titanium nitride layer using a chemical vapor deposition process performed at a second temperature that is greater than the first temperature with reactant gases of titanium chloride (TiCl4) gas and ammonia (NH3) gas.

Abstract translation: 一种制造存储电容器的方法包括使用化学气相沉积技术或在第一温度下用氯化钛（TiCl 4）气体和氨（NH 3））的反应气体进行的原子层沉积技术在电介质层上沉积第一氮化钛层， 气体以预定的流量比并且在第二氮化钛层上沉积第二氮化钛层，所述化学气相沉积工艺是在第二温度下用氯化钛（TiCl 4）气体和氨的反应气体 NH3）气体。

公开(公告)号：US07504725B2

公开(公告)日：2009-03-17

申请号：US10915871

申请日：2004-08-09

Applicant: Rak-Hwan Kim ,  Young-Cheon Kim ,  Hyeon-Deok Lee ,  Hyun-Young Kim ,  In-Sun Park

Inventor： Rak-Hwan Kim ,  Young-Cheon Kim ,  Hyeon-Deok Lee ,  Hyun-Young Kim ,  In-Sun Park

IPC: H01L23/52

CPC classification number: H01L23/485 ,  H01L21/28556 ,  H01L21/76841 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76876 ,  H01L27/10885 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device, in which a bit line can have a low resistance without an increase in the thickness of the bit line. In the semiconductor memory device, an insulating layer having a contact hole that exposes a conductive region is formed on a semiconductor substrate having the conductive region. A barrier metal layer is formed along the surface of the insulating layer and the surface of the contact hole. A grain control layer is formed between the barrier metal layer and the tungsten layer. A tungsten layer is formed on the grain control layer. A grain size of the tungsten layer is increased by the grain control layer.

Abstract translation: 一种半导体存储器件和半导体存储器件的制造方法，其中位线可以具有低电阻而不增加位线的厚度。 在半导体存储器件中，在具有导电区域的半导体衬底上形成具有暴露导电区域的接触孔的绝缘层。 沿着绝缘层的表面和接触孔的表面形成阻挡金属层。 在阻挡金属层与钨层之间形成晶粒控制层。 在晶粒控制层上形成钨层。 钨层的晶粒尺寸由晶粒控制层增加。

公开(公告)号：US07479434B2

公开(公告)日：2009-01-20

申请号：US11497362

申请日：2006-08-02

Applicant: Dong-Jo Kang ,  In-Sun Park ,  Dae-Joung Kim

Inventor： Dong-Jo Kang ,  In-Sun Park ,  Dae-Joung Kim

IPC: H01L21/336

CPC classification number: H01L21/823443 ,  H01L21/823418 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: A semiconductor device includes a gate structure formed on a substrate. The gate structure includes an uppermost first metal silicide layer pattern having a first thickness. Spacers are formed on sidewalls of the gate structure. One or more impurity regions are formed in the substrate adjacent to at least one sidewall of the gate structure. A second metal silicide layer pattern, having a second thickness thinner than the first thickness, is formed on the one or more impurity regions.

Abstract translation: 半导体器件包括形成在衬底上的栅极结构。 栅极结构包括具有第一厚度的最上面的第一金属硅化物层图案。 隔板形成在栅极结构的侧壁上。 在与栅极结构的至少一个侧壁相邻的衬底中形成一个或多个杂质区。 在一个或多个杂质区上形成具有比第一厚度薄的第二厚度的第二金属硅化物层图案。

公开(公告)号：US20080116437A1

公开(公告)日：2008-05-22

申请号：US11769532

申请日：2007-06-27

Applicant: Gyu-Hwan Oh ,  In-Sun Park ,  Hyun-Seok Lim ,  Ki-Jong Lee ,  Nak-Hyun Lim

Inventor： Gyu-Hwan Oh ,  In-Sun Park ,  Hyun-Seok Lim ,  Ki-Jong Lee ,  Nak-Hyun Lim

IPC: H01L47/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

Abstract: A phase change memory device includes a current restrictive element interposed between an electrically conductive element and a phase change material. The current restrictive element includes a plurality of overlapping film patterns, each of which having a respective first portion proximal to the conductive element and a second portion proximal to the phase change material. The second portions are configured and dimensioned to have higher resistance than the first portions.

Abstract translation: 相变存储器件包括介于导电元件和相变材料之间的电流限制元件。 电流限制元件包括多个重叠的膜图案，每个重叠的膜图案具有靠近导电元件的相应的第一部分和靠近相变材料的第二部分。 第二部分的构造和尺寸设计成具有比第一部分更高的电阻。