公开(公告)号：US08286021B2

公开(公告)日：2012-10-09

申请号：US11953385

申请日：2007-12-10

申请人： Yeon-Ho Kim ,  Kyeong-Han Lee ,  Jong-Hwa Kim ,  In-Young Kim ,  Young-Joon Choi ,  Seok-Cheon Kwon

发明人： Yeon-Ho Kim ,  Kyeong-Han Lee ,  Jong-Hwa Kim ,  In-Young Kim ,  Young-Joon Choi ,  Seok-Cheon Kwon

IPC分类号： G06F1/12 ,  G11C11/34

CPC分类号： G06F1/12 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/109 ,  G11C16/32

摘要： A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

摘要翻译： 闪速存储器件包括存储单元阵列，时钟信号输入端，用于接收指定写入操作模式的信号的输入端，多个数据输入/输出焊盘和数据输入/输出缓冲电路， 时钟信号输入和多个数据输入/输出焊盘。 数据输入/输出缓冲电路被配置为响应于信号的激活而与应用于时钟信号输入的时钟信号同步地通过数据输入/输出焊盘接收要写入存储单元阵列的数据 指定书写操作模式。

公开(公告)号：US08194463B2

公开(公告)日：2012-06-05

申请号：US12485983

申请日：2009-06-17

申请人： Jong-Hwa Kim ,  Seok-Cheon Kwon ,  Young-Joon Choi

发明人： Jong-Hwa Kim ,  Seok-Cheon Kwon ,  Young-Joon Choi

IPC分类号： G11C16/06 ,  G11C11/34

CPC分类号： G11C16/3454 ,  G11C16/3459

摘要： A programming method of a flash memory device having memory cells, and a flash memory device to perform the method, including programming selected memory cells according to loaded data, sensing states of the programmed memory cells and firstly latching the sensed states, and determining whether a program-inhibited memory cell among the selected memory cells has been programmed, with reference to the loaded data and the latched states, before determining whether the selected memory cells have been properly programmed.

摘要翻译： 一种具有存储单元的闪速存储器件的编程方法，以及执行该方法的闪速存储器件，包括根据加载的数据对所选择的存储器单元进行编程，感测编程的存储器单元的状态，并首先锁定感测的状态，以及确定是否 在确定所选择的存储器单元是否被正确地编程之前，参考所加载的数据和锁存状态，已编程所选存储单元中的程序禁止存储单元。

公开(公告)号：US07554850B2

公开(公告)日：2009-06-30

申请号：US11319307

申请日：2005-12-27

申请人： Jong-Hwa Kim

发明人： Jong-Hwa Kim

IPC分类号： G11C16/26 ,  G11C16/34

CPC分类号： G11C16/26 ,  G11C16/0483

摘要： We describe a nonvolatile memory device with a wired-OR structure and method of driving the same that reduces peak current during the wired-OR operation. The nonvolatile semiconductor memory device includes a memory cell array including a plurality of bitlines and a plurality of memory cells to store data. A plurality of page buffers buffer main latch data responsive to the bitlines. An internal output line operates in an output drive voltage responsive to the main latch data. A global output line transfers a data bit responsive to the internal output line. An output switch circuit electrically connects the global output line to the internal output line during a wired-OR operation. And a data line control circuit charges the global output line with a charge current after discharging the same during the wired-OR operation.

摘要翻译： 我们描述一种具有线OR结构的非易失性存储器件及其驱动方式，可在线或运算期间降低峰值电流。 非易失性半导体存储器件包括包括多个位线的存储单元阵列和用于存储数据的多个存储器单元。 多个页缓冲器响应于位线缓冲主锁存数据。 内部输出线响应于主锁存器数据而以输出驱动电压工作。 全局输出线响应于内部输出线传输数据位。 输出开关电路在布线或运算期间将全局输出线电连接到内部输出线路。 并且数据线控制电路在布线或运算期间对其放电后的充电电流对全局输出线充电。

公开(公告)号：US07535775B2

公开(公告)日：2009-05-19

申请号：US11586599

申请日：2006-10-26

申请人： Joo-Ah Kang ,  Jong-Hwa Kim

发明人： Joo-Ah Kang ,  Jong-Hwa Kim

IPC分类号： G11C7/10

CPC分类号： G06T1/60

摘要： A page buffer may comprise of a latch connected to a sense node at a first contact point. The page buffer may also comprise of a sensing circuit connected to the sense node at a second contact point, the sensing circuit being configured to sense cell data of the sense node. The page buffer may also comprise of a switch circuit which electrically connects the first contact point with the second contact point after the first contact point is charged by the latch.

摘要翻译： 页面缓冲器可以包括在第一接触点处连接到感测节点的锁存器。 页面缓冲器还可以包括在第二接触点处连接到感测节点的感测电路，感测电路被配置为感测感测节点的小区数据。 页面缓冲器还可以包括在第一接触点被锁存器充电之后将第一接触点与第二接触点电连接的开关电路。

公开(公告)号：US20080133604A1

公开(公告)日：2008-06-05

申请号：US11946274

申请日：2007-11-28

申请人： Jong-hwa KIM

发明人： Jong-hwa KIM

IPC分类号： G06F17/30

CPC分类号： H04L29/06027 ,  H04L65/4092 ,  H04L65/604 ,  H04L65/607 ,  H04N21/23614 ,  H04N21/4131 ,  H04N21/4348 ,  H04N21/435 ,  H04N21/43615 ,  H04N21/43632 ,  H04N21/8126

摘要： A basic device used in a linking of the basic device and an extended device includes an extended scene description manager parsing an extended scene descriptor, and a meta data delivery manager extracting meta data from a multimedia stream using the result of parsing and transmitting the extracted meta data to the extended device.

摘要翻译： 在基本设备和扩展设备的链接中使用的基本设备包括分析扩展场景描述符的扩展场景描述管理器，以及使用解析和传送所提取的元数据的结果从多媒体流中提取元数据的元数据传递管理器 数据到扩展设备。

公开(公告)号：US20070237184A1

公开(公告)日：2007-10-11

申请号：US11783515

申请日：2007-04-10

申请人： Jeong-hoon Park ,  Ga-hyun Ryu ,  Kyung-sun Cho ,  Sun-hee Youm ,  Sung-il Park ,  Jong-hwa Kim

发明人： Jeong-hoon Park ,  Ga-hyun Ryu ,  Kyung-sun Cho ,  Sun-hee Youm ,  Sung-il Park ,  Jong-hwa Kim

IPC分类号： H04H1/04

CPC分类号： H04H20/30 ,  H04H20/28 ,  H04H20/93 ,  H04H20/95 ,  H04H2201/20 ,  H04N21/235 ,  H04N21/2362 ,  H04N21/434 ,  H04N21/4345 ,  H04N21/435 ,  H04N21/64322

摘要： Provided are an apparatus and method for providing an Internet Protocol Datacasting (IPDC) service in a Digital Audio Broadcasting (DAB) system. A digital broadcasting transmission apparatus for providing an IPDC service includes an IPDC processing unit which generates IP packet data by packetizing data to be transmitted and generates information on a configuration of the IP packet data; a service linkage information (SLI) processing unit which generates SLI which is linkage information between the IP packet data and an IP bearer which delivers the IP packet data; and a transmitter which multiplexes and transmits the SLI and the IP packet data. Accordingly, by generating and using SLI for linking a DAB system and an IPDC system, the DAB system can effectively provide an IPDC service.

摘要翻译： 提供了一种用于在数字音频广播（DAB）系统中提供因特网协议数据广播（IPDC）服务的装置和方法。 用于提供IPDC业务的数字广播发送装置包括IPDC处理单元，其通过打包要发送的数据生成IP分组数据，并生成关于IP分组数据的配置的信息; 服务链接信息（SLI）处理单元，其生成作为IP分组数据和传送IP分组数据的IP承载之间的链接信息的SLI; 以及多路复用和发送SLI和IP分组数据的发射机。 因此，通过生成和使用用于链接DAB系统和IPDC系统的SLI，DAB系统可以有效地提供IPDC服务。

公开(公告)号：US07271853B2

公开(公告)日：2007-09-18

申请号：US10995337

申请日：2004-11-24

申请人： Woo Jin Song ,  Kyu Young Hwang ,  Hyun Chool Shin ,  Chung Hee Lee ,  Jong Hwa Kim

发明人： Woo Jin Song ,  Kyu Young Hwang ,  Hyun Chool Shin ,  Chung Hee Lee ,  Jong Hwa Kim

IPC分类号： H04N3/23 ,  H04N3/22 ,  H04N9/28

CPC分类号： H04N17/00 ,  G09G1/00 ,  G09G3/001 ,  G09G3/3413 ,  G09G2320/0693 ,  H04N3/2335 ,  H04N5/74 ,  H04N5/7408 ,  H04N9/28 ,  H04N9/3102

摘要： An apparatus and a method for correcting a distorted image is capable of correcting an optical distortion of an image and misconvergence by prewarping an inputted image without using a convergence yoke, and an image displayer using the same. The apparatus for correcting an image distortion for an image displayer in which an image signal is inputted to display an image on a screen and an image distortion is corrected, includes: a reference image generator for generating a predetermined reference image; a camera for inputting the reference image and photographing an image outputted on the screen; and a distortion information extracting unit for comparing the photographed image outputted from the camera and the reference image outputted from the reference image generator, and generating distortion correction information to correct a distortion of the photographed image in case that the image has been distorted.

摘要翻译： 用于校正失真图像的装置和方法能够通过预先输入图像而不使用会聚轭来校正图像的光学失真和失会聚，以及使用其的图像显示器。 用于校正其中输入图像信号以在屏幕上显示图像和图像失真的图像显示器的图像失真的装置被校正，包括：用于产生预定参考图像的参考图像生成器; 用于输入参考图像并拍摄在屏幕上输出的图像的照相机; 以及失真信息提取单元，用于比较从照相机输出的拍摄图像和从参考图像生成器输出的参考图像，并且在图像失真的情况下产生失真校正信息以校正拍摄图像的失真。

公开(公告)号：US20070041247A1

公开(公告)日：2007-02-22

申请号：US11347223

申请日：2006-02-06

申请人： Joo-Ah Kang ,  Jong-Hwa Kim

发明人： Joo-Ah Kang ,  Jong-Hwa Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/08

摘要： A flash memory device is disclosed that comprises memory cells, a common node, a sense node connected to a selected bit line, a first register connected to the common node, and a second register connected to the common node and the sense node. The flash memory device further comprises a common sense circuit connected to the common node, the sense node, and a control node; a switch, and a pre-charge circuit connected to the control node and configured to pre-charge the control node.

摘要翻译： 公开了一种闪速存储器件，其包括存储器单元，公共节点，连接到所选位线的感测节点，连接到公共节点的第一寄存器以及连接到公共节点和感测节点的第二寄存器。 闪速存储装置还包括连接到公共节点，感测节点和控制节点的公共电路; 开关和连接到控制节点并被配置为对控制节点预充电的预充电电路。

公开(公告)号：US20070002631A1

公开(公告)日：2007-01-04

申请号：US11416320

申请日：2006-05-03

申请人： Joo-Ah Kang ,  Jong-Hwa Kim ,  Moo-Sung Kim

发明人： Joo-Ah Kang ,  Jong-Hwa Kim ,  Moo-Sung Kim

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3413 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642

摘要： In one aspect, a non-volatile memory device includes a non-volatile memory cell array and a page buffer. The page buffer includes a sense node selectively connected to a bit line of the memory cell array, a main latch circuit including first and second main latch nodes, where the first main latch node is selectively connected to the sense node, and a latch input node selectively connected to the first and second main latch nodes. The page buffer further includes a cache latch circuit including first and second cache latch nodes, a switching circuit which selectively connects the second cache latch node to the latch input node, and a shared sense circuit connected between to the latch input node and a reference potential. The shared sense circuit selectively connects the latch input node to the reference potential in response to a voltage of the sense node and a voltage of the first cache latch node.

摘要翻译： 一方面，非易失性存储器件包括非易失性存储单元阵列和页缓冲器。 页面缓冲器包括选择性地连接到存储单元阵列的位线的感测节点，包括第一和第二主锁存节点的主锁存电路，其中第一主锁存节点选择性地连接到感测节点，以及锁存输入节点 选择性地连接到第一和第二主锁存节点。 页面缓冲器还包括一个包括第一和第二高速缓存锁存节点的高速缓存锁存电路，一个选择性地将第二高速缓存锁存节点连接到锁存输入节点的切换电路，以及连接到锁存器输入节点和参考电位之间的共享检测电路 。 响应于感测节点的电压和第一高速缓存锁存器节点的电压，共享感测电路选择性地将锁存器输入节点连接到参考电位。

公开(公告)号：US07154789B2

公开(公告)日：2006-12-26

申请号：US10977426

申请日：2004-10-28

申请人： Jong-Hwa Kim ,  Dae-Seok Byeon

发明人： Jong-Hwa Kim ,  Dae-Seok Byeon

IPC分类号： G11C5/14

CPC分类号： H02M3/073 ,  H02M2001/0041

摘要： According to embodiments of the invention, a high-voltage generator circuit may include a voltage detector block that has a voltage divider, a discharge section, a comparator, and a control signal generator. The voltage divider generates a divided voltage at an output node by dividing a high voltage. The discharge section discharges the high voltage to a power voltage in response to a first control signal. The comparator determines whether the divided voltage reaches a reference voltage, and the control signal generator generates a second control signal in response to an output from the comparator and the first control signal. The voltage divider may include a high-voltage prevention circuit that prevents the high voltage from being applied to a low-voltage transistor of the comparator during a discharge period of the high voltage. The high-voltage prevention circuit may include a depletion-type or enhancement-type NMOS transistor having a high breakdown voltage.

摘要翻译： 根据本发明的实施例，高压发生器电路可以包括具有分压器，放电部分，比较器和控制信号发生器的电压检测器块。 分压器通过分压高电压在输出节点产生分压。 放电部分响应于第一控制信号将高电压放电到电源电压。 比较器确定分压是否达到参考电压，并且控制信号发生器响应于比较器的输出和第一控制信号产生第二控制信号。 分压器可以包括高电压防止电路，其在高电压的放电期间防止高电压施加到比较器的低压晶体管。 高压防止电路可以包括具有高击穿电压的耗尽型或增强型NMOS晶体管。