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130 条记录 (耗时 0.033 秒)

    HIGH EFFICIENCY LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME
    63.
    发明申请
    HIGH EFFICIENCY LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME 有权
    高效发光二极管及其制造方法

    公开(公告)号：US20110241045A1

    公开(公告)日：2011-10-06

    申请号：US13018557

    申请日：2011-02-01

    申请人： Kyung Hee YE ,  Chang Youn KIM ,  Jin Cheol SHIN ,  Joon Hee LEE ,  Jong Kyun YOU ,  Hong Chol LIM

    发明人： Kyung Hee YE ,  Chang Youn KIM ,  Jin Cheol SHIN ,  Joon Hee LEE ,  Jong Kyun YOU ,  Hong Chol LIM

    IPC分类号： H01L33/46

    CPC分类号： H01L33/46 ,  H01L33/0079 ,  H01L33/20 ,  H01L33/22 ,  H01L33/24 ,  H01L33/387 ,  H01L33/42 ,  H01L33/44

    摘要： A high-efficiency light emitting diode including: a semiconductor stack positioned on a support substrate, including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; an insulating layer disposed in an opening that divides the p-type compound semiconductor layer and active layer; a transparent electrode layer disposed on the insulating layer and the p-type compound semiconductor layer; a reflective insulating layer covering the transparent electrode layer, to reflect light from the active layer away from the support substrate; a p-electrode covering the reflective insulating layer; and an n-electrode is formed on top of the n-type compound semiconductor layer. The p-electrode is electrically connected to the transparent electrode layer through the insulating layer.

    摘要翻译： 一种高效率发光二极管，包括：位于支撑基板上的半导体堆叠，包括p型化合物半导体层，有源层和n型化合物半导体层; 设置在分隔所述p型化合物半导体层和有源层的开口中的绝缘层; 设置在绝缘层和p型化合物半导体层上的透明电极层; 覆盖所述透明电极层的反射绝缘层，以将来自所述有源层的光反射离开所述支撑基板; 覆盖反射绝缘层的p电极; 并且在n型化合物半导体层的顶部上形成n电极。 p电极通过绝缘层与透明电极层电连接。

    Semiconductor devices including line patterns separated by cutting regions
    64.
    发明授权
    Semiconductor devices including line patterns separated by cutting regions 有权
    半导体器件包括由切割区分开的线图案

    公开(公告)号：US07898007B2

    公开(公告)日：2011-03-01

    申请号：US11961551

    申请日：2007-12-20

    申请人： Sung-Bok Lee ,  Joon-Hee Lee

    发明人： Sung-Bok Lee ,  Joon-Hee Lee

    IPC分类号： H01L23/52

    CPC分类号： H01L27/11568 ,  H01L27/0207 ,  H01L27/115

    摘要： Semiconductor devices are provided. A semiconductor device can include a substrate and a plurality of dummy line patterns on the substrate that extend in a first direction parallel with one another. Each of the dummy line patterns can include a plurality of sub-line patterns aligned along the first direction and which are separated from each other by at least one cutting region therebetween. The dummy line patterns can include first and second dummy line patterns which are adjacent to each other in a second direction that is perpendicular to the first direction. At least one of the cutting regions between a pair of sub-line patterns of the first dummy line pattern is aligned with and bounded by one of the sub-line patterns of the second dummy line pattern in the second direction.

    摘要翻译： 提供半导体器件。 半导体器件可以包括衬底和在基板上的彼此平行的第一方向上延伸的多个虚拟线图案。 虚线图案中的每一个可以包括沿着第一方向排列的多个子线图案，并且通过其间的至少一个切割区域彼此分离。 假线图案可以包括在垂直于第一方向的第二方向上彼此相邻的第一和第二假线图案。 第一虚线图案的一对子线图案之间的切割区域中的至少一个与第二虚线图案的第二方向上的一条子线图形对准并限定在第二方向上。

    Memory module and memory system having the same
    65.
    发明授权
    Memory module and memory system having the same 有权
    内存模块和内存系统具有相同的功能

    公开(公告)号：US07583509B2

    公开(公告)日：2009-09-01

    申请号：US11325083

    申请日：2006-01-04

    申请人： In-su Choi ,  Joon-hee Lee ,  Hee-joo Choi ,  Il-guy Jung

    发明人： In-su Choi ,  Joon-hee Lee ,  Hee-joo Choi ,  Il-guy Jung

    IPC分类号： H05K1/00

    CPC分类号： G11C5/063 ,  G11C5/04 ,  H05K1/148 ,  H05K2201/10159

    摘要： A memory module and a memory system are provided. The memory module includes a first circuit board on which at least one memory chip is mounted, a second circuit board on which at least one memory chip is mounted, and a flexible coupler electrically connecting the first circuit board to the second circuit board. The memory module is bendable and is configured to extend around a memory controller. The memory chips are electrically coupled with the memory controller via a respective plurality of signal lines. The bendable memory module is configured to be bent around the memory controller such that respective lengths of the signal lines are equal.

    摘要翻译： 提供了存储器模块和存储器系统。 存储器模块包括其上安装有至少一个存储器芯片的第一电路板，安装至少一个存储器芯片的第二电路板和将第一电路板电连接到第二电路板的柔性耦合器。 存储器模块是可弯曲的并且被配置为围绕存储器控制器延伸。 存储器芯片通过相应的多个信号线与存储器控制器电耦合。 可弯曲存储器模块被配置为围绕存储器控制器弯曲，使得信号线的相应长度相等。

    Method and apparatus to negotiate channel sharing in PLC network
    66.
    发明申请
    Method and apparatus to negotiate channel sharing in PLC network 审中-公开
    在PLC网络中协商通道共享的方法和装置

    公开(公告)号：US20070230497A1

    公开(公告)日：2007-10-04

    申请号：US11705454

    申请日：2007-02-13

    申请人： Jun-hae Choi ,  Joon-hee Lee ,  Ju-han Lee ,  Hyun-ah Sung ,  In-hwan Kim ,  Ho-Jeong You

    发明人： Jun-hae Choi ,  Joon-hee Lee ,  Ju-han Lee ,  Hyun-ah Sung ,  In-hwan Kim ,  Ho-Jeong You

    IPC分类号： H04B7/212

    CPC分类号： H04B3/542 ,  H04B2203/5408 ,  H04B2203/5445 ,  H04L12/413 ,  H04L12/417 ,  Y02D70/10

    摘要： A method of negotiating channel sharing between adjacent cells when there are a plurality of cells in a power line communication (PLC) network. The method includes attempting to negotiate the channel sharing during a minimum contention access period (CAP) which starts after a maximum beacon period ends and ends before a CAP of each PLC cell ends, wherein the maximum beacon period indicates a maximum size that a beacon frame in a super-frame transmitted from a coordinator of each PLC cell can have. When an attempt to negotiate the channel sharing is made using this method, interference does not occur during channel sharing negotiation, and effective channel sharing can be achieved, thereby eliminating interference between adjacent cells.

    摘要翻译： 当在电力线通信（PLC）网络中存在多个小区时，协商相邻小区之间的信道共享的方法。 该方法包括尝试在最小竞争访问周期（CAP）之间协商信道共享，该最小竞争接入周期（CAP）在最大信标周期结束之后开始，并且在每个PLC小区的CAP结束之前结束，其中最大信标周期指示信标帧 在从每个PLC单元的协调器发送的超帧中可以具有。 当使用该方法尝试协商信道共享时，在信道共享协商期间不会发生干扰，并且可以实现有效的信道共享，从而消除相邻小区之间的干扰。

    Non-volatile memory devices having floating gates and related methods of forming the same
    67.
    发明申请
    Non-volatile memory devices having floating gates and related methods of forming the same 失效
    具有浮动栅极的非易失性存储器件及其相关方法

    公开(公告)号：US20070108498A1

    公开(公告)日：2007-05-17

    申请号：US11594327

    申请日：2006-11-08

    申请人： Joon-Hee Lee ,  Jong-Ho Park ,  Jin-Hyun Shin ,  Sung-Hoi Hur ,  Yong-Seok Kim ,  Jong-Won Kim

    发明人： Joon-Hee Lee ,  Jong-Ho Park ,  Jin-Hyun Shin ,  Sung-Hoi Hur ,  Yong-Seok Kim ,  Jong-Won Kim

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.

    摘要翻译： 非易失性存储器件可以包括具有单元区域的衬底和在衬底的单元区域上的单元器件隔离层，以限定电池活性区域。 浮置栅极可以包括顺序堆叠在单元有源区上的下浮置栅极和上浮置栅极，并且隧道绝缘图案可以在浮栅和电池有源区之间。 控制栅极电极可以在浮置栅极上，并且阻挡绝缘图案可以在控制栅电极和浮栅之间。 更具体地说，上部浮动栅极可以包括在下部浮动栅极上的平坦部分和从邻近电池器件隔离层的平坦部分的两个边缘向上延伸的一对壁部分。 此外，由平坦部分和一对壁部分围绕的空间的上部的宽度可以大于空间的下部的宽度。 还讨论了相关方法。

    Chemical mechanical polishing (CMP) apparatus and CMP method using the same
    69.
    发明授权
    Chemical mechanical polishing (CMP) apparatus and CMP method using the same 失效
    化学机械抛光（CMP）装置和使用其的CMP方法

    公开(公告)号：US5837610A

    公开(公告)日：1998-11-17

    申请号：US805659

    申请日：1997-02-27

    申请人： Byoung-hun Lee ,  Joon-hee Lee

    发明人： Byoung-hun Lee ,  Joon-hee Lee

    IPC分类号： B24B1/00 ,  B24B37/00 ,  B24B37/20 ,  B24B37/24 ,  B24B57/02 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105

    CPC分类号： B24B57/02 ,  B24B37/04 ,  H01L21/31051

    摘要： A chemical mechanical polishing (CMP) apparatus for planarizing a semiconductor wafer includes a wafer carrier for loading and fixing a semiconductor wafer to be polished and a polishing platen rotating at a constant speed, disposed at a lower portion of the wafer carrier. A polishing pad is provided on an upper surface of the polishing platen, and is in contact with a surface of the semiconductor wafer. A spiral slurry feed line supplies a slurry solution to the polishing pad. An end of the spiral slurry feed line is provided with a plurality of nozzles and the spiral slurry feed line is connected to a deionized water feed line that is opened or closed by a valve. Accordingly, abrasives are prevented from being precipitated, and the slurry solution is uniformly supplied to the semiconductor wafer, to thereby enhance polishing uniformity.

    摘要翻译： 用于平坦化半导体晶片的化学机械抛光（CMP）装置包括用于加载和固定待抛光的半导体晶片的晶片载体和设置在晶片载体的下部的以恒定速度旋转的研磨平板。 抛光垫设置在研磨台板的上表面上并与半导体晶片的表面接触。 螺旋浆料进料管线将浆液提供给抛光垫。 螺旋浆料供给管线的端部设置有多个喷嘴，并且螺旋浆料进料管线连接到由阀打开或关闭的去离子水进料管线。 因此，防止了研磨剂的沉淀，将浆液溶液均匀地供给到半导体晶片，从而提高了研磨均匀性。