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    Method and apparatus for coordinating dynamic memory deallocation with a redundant bit line steering mechanism
    61.
    发明申请
    Method and apparatus for coordinating dynamic memory deallocation with a redundant bit line steering mechanism 失效
    用于协调动态内存释放与冗余位线转向机制的方法和装置

    公开(公告)号：US20050028039A1

    公开(公告)日：2005-02-03

    申请号：US10631067

    申请日：2003-07-31

    申请人： Daniel Henderson ,  Alongkorn Kitamorn ,  Wayne Lemmon ,  Naresh Nayar ,  Ravi Shankar

    发明人： Daniel Henderson ,  Alongkorn Kitamorn ,  Wayne Lemmon ,  Naresh Nayar ,  Ravi Shankar

    IPC分类号： G06F11/00 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42

    CPC分类号： G11C29/42 ,  G06F11/106 ,  G11C29/70 ,  G11C2029/0409

    摘要： A method and apparatus for coordinating dynamic memory page deallocation with a redundant bit line steering mechanism are provided. With the method and apparatus, memory scrubbing and redundant bit line steering operations are performed in parallel with handling of notifications of runtime correctable errors. When a correctable error is encountered during runtime, and the correctable error is determined to be persistent, then dynamic memory page deallocation is requested of a hypervisor. The determination of persistence is based on a history CE table that is populated by the operation of the memory scrubbing and redundant bit line steering mechanism of a service processor. Thus, only those correctable errors that persist for longer than one memory scrubbing cycle are subject to memory page deallocation.

    摘要翻译： 提供了一种用于与冗余位线转向机构协调动态存储器页面解除分配的方法和装置。 利用该方法和装置，与处理运行时可校正错误的通知并行执行存储器擦除和冗余位线转向操作。 当在运行时遇到可纠正的错误，并且确定可纠正的错误是持久的，则请求虚拟机管理程序的动态内存页解除分配。 持久性的确定基于由服务处理器的存储器擦除和冗余位线转向机制的操作填充的历史CE表。 因此，只有那些持续时间超过一个内存擦除周期的可纠正错误才会受到内存页解除分配。

    Multiple page size segment encoding
    63.
    发明授权
    Multiple page size segment encoding 有权
    多页大小段编码

    公开(公告)号：US08745307B2

    公开(公告)日：2014-06-03

    申请号：US12779563

    申请日：2010-05-13

    申请人： Sundeep Chadha ,  Cathy May ,  Naresh Nayar ,  Randal Craig Swanberg

    发明人： Sundeep Chadha ,  Cathy May ,  Naresh Nayar ,  Randal Craig Swanberg

    IPC分类号： G06F12/00 ,  G06F12/10

    CPC分类号： G06F12/1018 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/652

    摘要： An approach identifies an amount of high order bits used to store a memory address in a memory address field that is included in a memory. This approach calculates at least one minimum number of low order bits not used to store the address with the calculation being based on the identified amount of high order bits. The approach retrieves a data element from one of the identified minimum number of low order bits of the address field and also retrieves a second data element from one of the one of the identified minimum number of low order bits of the address field.

    摘要翻译： 一种方法识别用于在存储器中包括的存储器地址字段中存储存储器地址的高位数量。 该方法计算不用于存储地址的至少一个最低数量的低阶位，其中计算基于所识别的高位位数。 该方法从所识别的地址字段的最低位数的最低位数中的一个中检索数据元素，并且还从所识别的地址字段的最低位数中的一个中检索第二数据元素。

    PROVIDING LOGICAL PARTIONS WITH HARDWARE-THREAD SPECIFIC INFORMATION REFLECTIVE OF EXCLUSIVE USE OF A PROCESSOR CORE
    64.
    发明申请
    PROVIDING LOGICAL PARTIONS WITH HARDWARE-THREAD SPECIFIC INFORMATION REFLECTIVE OF EXCLUSIVE USE OF A PROCESSOR CORE 审中-公开
    提供具有硬件特征信息的逻辑分段反映处理器核心的独家使用

    公开(公告)号：US20130179886A1

    公开(公告)日：2013-07-11

    申请号：US13452745

    申请日：2012-04-20

    申请人： Giles R. Frazier ,  Bruce Mealy ,  Naresh Nayar

    发明人： Giles R. Frazier ,  Bruce Mealy ,  Naresh Nayar

    IPC分类号： G06F9/46

    CPC分类号： G06F21/6218 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/45541 ,  G06F9/45558 ,  G06F2009/45587

    摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

    摘要翻译： 用于模拟在多个逻辑分区（LPAR）中独占使用处理器核心的技术包括提供响应于LPAR的访问请求的硬件线程依赖状态信息，所述LPAR反映了LPAR访问硬件线程相关的独占使用处理器 信息。 如果请求者是在低于管理程序权限级别的特权级别下执行的程序，则转换响应于访问请求而返回的信息，使得每个逻辑分区将处理器视为处理器的独占使用。 这些技术可以由处理器核心内的逻辑电路块来实现，其将硬件线程特定信息转换为硬件线程特定信息的逻辑表示，或者可以通过将访问陷阱的中断处理程序的程序指令执行 物理寄存器包含信息。

    Transparently increasing power savings in a power management environment
    65.
    发明授权
    Transparently increasing power savings in a power management environment 有权
    在电源管理环境中透明地增加功耗

    公开(公告)号：US08423811B2

    公开(公告)日：2013-04-16

    申请号：US13457030

    申请日：2012-04-26

    申请人： Naresh Nayar ,  Karthik Rajamani ,  Freeman L. Rawson, III

    发明人： Naresh Nayar ,  Karthik Rajamani ,  Freeman L. Rawson, III

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3203 ,  G06F9/5077 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/36

    摘要： A mechanism is provided for transparently consolidating resources of logical partitions. Responsive to the existence of the non-folded resource on an originating resource chip, the virtualization mechanism determines whether there is a destination resource chip to either exchange operations of the non-folded resource with a folded resource on the destination chip or migrate operations of the non-folded resource to a non-folded resource on the destination chip. Responsive to the existence of the folded resource on the destination resource chip, the virtualization mechanism transparently exchanges the operations of the non-folded resource from the originating resource chip to the folded resource on the destination resource chip, where the folded resource remains folded on the originating resource chip after the exchange. Responsive to the absence of another non-folded resource on the originating resource chip, the vitalization mechanism places the originating resource chip into a deeper power saving mode.

    摘要翻译： 提供了一种用于透明地整合逻辑分区资源的机制。 响应于原始资源芯片上的非折叠资源的存在，虚拟化机制确定是否存在目的地资源芯片，以在目的地芯片上用折叠资源来交换非折叠资源的操作，或者迁移操作 非折叠资源到目标芯片上的非折叠资源。 响应于目标资源芯片上折叠资源的存在，虚拟化机制透明地将未折叠资源的操作从始发资源芯片交换到目的地资源芯片上的折叠资源，其中折叠资源保持折叠在 交换后的源资源芯片。 响应于起始资源芯片上不存在另一非折叠资源，激活机制将始发资源芯片置于更深的省电模式。

    PRIVILEGE LEVEL AWARE PROCESSOR HARDWARE RESOURCE MANAGEMENT FACILITY
    66.
    发明申请
    PRIVILEGE LEVEL AWARE PROCESSOR HARDWARE RESOURCE MANAGEMENT FACILITY 有权
    特权级注意处理器硬件资源管理设施

    公开(公告)号：US20130086581A1

    公开(公告)日：2013-04-04

    申请号：US13251879

    申请日：2011-10-03

    申请人： Giles R. Frazier ,  Michael K. Gschwind ,  Naresh Nayar

    发明人： Giles R. Frazier ,  Michael K. Gschwind ,  Naresh Nayar

    IPC分类号： G06F9/455

    CPC分类号： G06F9/45533 ,  G06F9/45558 ,  G06F9/462 ,  G06F9/5077 ,  G06F2009/45579

    摘要： Multiple machine state registers are included in a processor core to permit distinction between use of hardware facilities by applications, supervisory threads and the hypervisor. All facilities are initially disabled by the hypervisor when a partition is initialized. When any access is made to a disabled facility, the hypervisor receives an indication of which facility was accessed and sets a corresponding hardware flag in the hypervisor's machine state register. When an application attempts to access a disabled facility, the supervisor managing the operating system image receives an indication of which facility was accessed and sets a corresponding hardware flag in the supervisor's machine state register. The multiple register implementation permits the supervisor to determine whether particular hardware facilities need to have their state saved when an application context swap occurs and the hypervisor can determine which hardware facilities need to have their state saved when a partition swap occurs.

    摘要翻译： 多个机器状态寄存器被包括在处理器核心中，以便区分应用程序，监督线程和管理程序之间的硬件设施的使用。 当初始化分区时，所有的设备最初被管理程序禁用。 当对残疾设施进行访问时，管理程序将收到访问哪个设施的指示，并在管理程序的机器状态寄存器中设置相应的硬件标志。 当应用程序尝试访问禁用的设备时，管理操作系统映像的主管接收到哪个设备被访问的指示，并在主管机器状态寄存器中设置相应的硬件标志。 多寄存器实现允许主管当发生应用程序上下文交换时确定特定硬件设施是否需要保存其状态，并且管理程序可以确定在发生分区交换时哪些硬件设施需要保存其状态。

    Controlling Depth and Latency of Exit of a Virtual Processor's Idle State in a Power Management Environment
    67.
    发明申请
    Controlling Depth and Latency of Exit of a Virtual Processor's Idle State in a Power Management Environment 失效
    控制电源管理环境中虚拟处理器空闲状态退出的深度和延迟

    公开(公告)号：US20110154323A1

    公开(公告)日：2011-06-23

    申请号：US12645597

    申请日：2009-12-23

    申请人： Richard L. Arndt ,  Naresh Nayar ,  Christopher Francois ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Randal C. Swanberg

    发明人： Richard L. Arndt ,  Naresh Nayar ,  Christopher Francois ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Randal C. Swanberg

    IPC分类号： G06F9/455

    CPC分类号： G06F9/45533 ,  G06F9/45541 ,  G06F2009/45575

    摘要： A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.

    摘要翻译： 在逻辑分区的数据处理系统中提供一种机制，用于控制虚拟处理器的空闲状态的退出的深度和等待时间。 一个虚拟化层产生一个雪松延迟设置信息（CLSI）数据。 响应于引导逻辑分区，虚拟化层将CLSI数据传送到逻辑分区的操作系统（OS）。 OS根据CLSI数据确定在OS控制下的虚拟处理器的特定空闲状态。 响应于调用虚拟化层的OS，OS将虚拟处理器的特定空闲状态传送到虚拟化层，以将特定的空闲状态和唤醒特性分配给虚拟处理器。

    Preserving a Dedicated Temporary Allocation Virtualization Function in a Power Management Environment
    68.
    发明申请
    Preserving a Dedicated Temporary Allocation Virtualization Function in a Power Management Environment 有权
    在电源管理环境中保留专用的临时分配虚拟化功能

    公开(公告)号：US20110154322A1

    公开(公告)日：2011-06-23

    申请号：US12644749

    申请日：2009-12-22

    申请人： Naresh Nayar ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Malcolm S. Ware

    发明人： Naresh Nayar ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Malcolm S. Ware

    IPC分类号： G06F9/455 ,  G06F9/46

    CPC分类号： G06F9/45533 ,  G06F1/324 ,  G06F9/5077 ,  G06F9/5094 ,  G06F2209/5011 ,  Y02D10/126 ,  Y02D10/22 ,  Y02D10/26 ,  Y02D10/28 ,  Y02D10/36

    摘要： A mechanism is provided for temporarily allocating dedicated processors to a shared processor pool. A virtual machine monitor determines whether a temporary allocation associated with an identified dedicated processor is long-term or short-term. Responsive to the temporary allocation being long-term, the virtual machine monitor determines whether an operating frequency of the identified dedicated processor is within a predetermined threshold of an operating frequency of one or more operating systems utilizing the shared processor pool. Responsive to the operating frequency of the identified dedicated processor failing to be within the predetermined threshold, the virtual machine monitor either increases or decreases the frequency of the identified dedicated processor to be within the predetermined threshold of the operating frequency of the one or more operating systems utilizing the shared processor pool and temporarily allocates the identified dedicated processor to the shared processor pool.

    摘要翻译： 提供了一种用于将专用处理器临时分配给共享处理器池的机制。 虚拟机监视器确定与所识别的专用处理器相关联的临时分配是长期的还是短期的。 响应于长期的临时分配，虚拟机监视器确定所识别的专用处理器的工作频率是否在利用共享处理器池的一个或多个操作系统的操作频率的预定阈值内。 响应于所识别的专用处理器的操作频率不能在预定阈值内，虚拟机监视器将所识别的专用处理器的频率增加或降低在一个或多个操作系统的操作频率的预定阈值内 利用共享处理器池并临时将识别的专用处理器分配给共享处理器池。

    Processor and Memory Folding for Energy Management
    69.
    发明申请
    Processor and Memory Folding for Energy Management 失效
    处理器和内存折叠用于能源管理

    公开(公告)号：US20110154083A1

    公开(公告)日：2011-06-23

    申请号：US12642098

    申请日：2009-12-18

    申请人： Richard L. Arndt ,  Naresh Nayar ,  Freeman L. Rawson, III ,  Randal C. Swanberg

    发明人： Richard L. Arndt ,  Naresh Nayar ,  Freeman L. Rawson, III ,  Randal C. Swanberg

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3203

    摘要： A method, system and computer-usable medium are disclosed for managing power consumption in information processing systems. Processing resources are successively folded, allowing them to be placed into deeper and deeper power saving states while maintaining the ability to respond to new processing loads without exposing the latency of the deeper power saving states as they are unfolded. Before a deeper power saving state can be used, there must be sufficient processing resources in the prior power saving state to mask the latency of bringing a processing resource out of the deeper power saving state.

    摘要翻译： 公开了一种用于管理信息处理系统中的功耗的方法，系统和计算机可用介质。 处理资源被连续地折叠，使得它们能够被放置在更深和更深的省电状态，同时保持对新的处理负载的响应能力，而不会暴露更深的省电状态在其展开时的延迟。 在可以使用更深的省电状态之前，在现有的省电状态下必须有足够的处理资源，以掩盖使处理资源脱离更深的省电状态的延迟。